Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
1999-10-27
2001-09-18
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S189050, C365S230080, C365S233100, C365S194000
Reexamination Certificate
active
06292410
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an apparatus for receiving an external data strobe signal in a high-speed memory device to generate internal data strobe signals used in a write operation therein, capable of preventing an erroneous operation thereof and obtaining a sufficient operating margin.
DESCRIPTION OF THE PRIOR ART
As is well known those skilled in the art, a synchronous dynamic random access memory (SDRAM) is widely used for improving an operating speed. The SDRAM operates at high speed under synchronization of a system clock inputted from an external DRAM controller, wherein the system clock is also called a data strobe signal. The typical SDRAM employs pulse signals which are synchronized on a rising edge of the data strobe signal. On the other hand, Double Data Rate SDRAM (hereinafter, referred to as DDR SDRAM) employs two kinds of pulse signals which are respectively synchronized on a rising edge and a falling edge of the data strobe signal, so that it supplies a more high-speed operating speed than the typical SDRAM. Therefore, the DDR SDRAM requires two kinds of apparatus (hereinafter, referred to as a data strobe buffer) for generating the pulse signals which are respectively synchronized on the falling edge as well as a rising edge of the data strobe signal.
Since each apparatus has a different circuit configuration each other, however, each delay time may also be different from each other, so that a different time shift occurs on the rising and falling edges of the data strobe signal. Therefore, it is difficult to obtain a sufficient operation margin. Further, in section “A” shown in
FIG. 1
, undesirable pulse signals should be prevented from being generated at a point when an enable signal EN for enabling the data strobe buffer is activated.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an apparatus for an apparatus for receiving an external data strobe signal to generate an internal data strobe signal in a high-speed memory device, thereby being capable of preventing an erroneous operation thereof and obtaining a sufficient operating margin.
In accordance with an embodiment of the present invention, there is provided an apparatus for receiving an external data strobe signal in a high-speed memory device to generate an internal data strobe signal used in a write operation therein, comprising: first buffering means, activated by an enable signal, for receiving the external data strobe signal having a series of pulses to output a first internal data strobe signal having a series of pulses, each pulse of the first internal data strobe signal corresponding to a rising edge of each pulse of the external data strobe signal; and second buffering means, activated by the enable signal, for receiving the external data strobe signal having a series of pulses to output a second internal data strobe signal having a series of pulses, each pulse of the second internal data strobe signal corresponding to a falling edge of each pulse of the external data strobe signal, wherein a delay to a corresponding pulse of the first internal data strobe signal from a rising edge of each pulse of the external data strobe signal is substantially identical to a delay to a corresponding pulse of the second internal data strobe signal from a falling edge of each pulses of the external data strobe signal.
REFERENCES:
patent: 6064625 (2000-05-01), Tomita
patent: 6078546 (2000-06-01), Lee
patent: 6151272 (2000-11-01), La et al.
Yi Seung-Hyun
Yoon Min-Ho
Jacobson & Holman PLLC
Kyundai Electronics Industries Co., Ltd.
Nelms David
Yoha Connie C.
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