Semiconductor gate trench with covered open ends

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S329000, C257S332000, C257S333000, C257S334000

Reexamination Certificate

active

06239464

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a trench-gate type semiconductor device and a fabrication method thereof, and more particularly to a transistor, which has open ends of trenches made of materials having a different oxidation rate, and a fabrication method thereof.
2. Description of the Related Art
A high integrated circuit, which has semiconductor devices such as transistors highly integrated by a micromachining technology, is demanded to be more densely integrated and have high driving performance.
In recent years, a semiconductor device having trenches (grooves) is particularly attracting attention. By forming gates so to have a trench configuration, an area occupied by the gates on a substrate can be decreased, resulting in achieving a high integrated circuit which has a high current value and high performance.
However, such a trench configuration has a drawback that a gate oxidation film on the open ends of the trenches is thinner than the other portion of the gate oxidation film. This is because the film grows differently in parts depending on its orientation during the thermal oxidation of the film. In a process for manufacturing a transistor, the oxidation of the gates requires a temperature of about 1000° C. Therefore, the gate oxidization film of the open ends becomes thin. When the gate oxidation film on the open ends of the trenches is thinner than the gate oxidization film on the other portion, it may be broken due to a high electric field generated on the open ends.
Where the oxidation is made at a temperature higher than 1000° C., the gate oxidation film is uniformly formed including the open ends of the trenches. But, the oxidation at a temperature higher than 1000° C. involves a disadvantage that impurities are excessively dispersed in an impurity dispersion layer.
A semiconductor device having a conventional trench configuration and a fabrication method thereof will be described with reference to FIG.
9
through FIG.
13
.
FIG. 9
is a plan diagram showing a conventional semiconductor device comprising a gate electrode extension section
11
, a source
3
and trenches
7
.
FIG. 10
is a sectional diagram taken along line A-A′ of
FIG. 9
, and
FIG. 11
is a sectional diagram taken along line B-B′ of FIG.
1
. They show a semiconductor substrate (drain)
1
, a base
2
, a gate film
8
and a gate electrode
10
as well as the gate electrode extension section
11
and the source
3
.
FIGS. 12A
to
12
D show a process for fabricating a conventional trench-gate type semiconductor device.
FIG. 12A
is a diagram showing that the base
2
, the source
3
and a thermal oxidation film
4
are formed on the silicon substrate (drain)
1
.
FIG. 12B
shows that a trench masking material
6
is formed on the thermal oxidation film
4
to etch trenches.
FIG. 12C
shows a state that the trenches
7
are formed in the semiconductor substrate by etching, and the thermal oxidation film
4
and the masking material
6
are removed.
FIG. 12D
shows that a gate film
8
is formed to cover the trenches
7
, the base
2
and the source
3
, and the gate electrode
10
is formed on the gate film.
FIG. 13
is an enlarged sectional diagram showing a trench configuration of a conventional semiconductor device. It is seen from
FIG. 13
that the gate film is thin as if it was notched at both ends of the open surface of the trench. An electric field tends to concentrate on the notched portions
12
where the gate film is thin, resulting in degrading a withstand pressure of the gate.
In order to remedy the above-described disadvantage involved in the trench configuration, a variety of attempts are being made.
For example, Japanese Patent Laid-Open Application No. Hei
7-249768
discloses a semiconductor device having the thickened upper end corners of trench side walls by oxidizing increasingly. Japanese Patent Laid-Open Application No. Hei
5-47919
discloses a semiconductor device which is formed to have round edges on trenches where elements are formed. Japanese Patent Laid-Open Application No. Hei
7-326738
discloses a configuration that the upper corners of trenches are not covered with the gate electrode. Japanese Patent Laid-Open Application No. Hei
2-113548
discloses a configuration that stepped sections are formed just below the gate electrode, and an oxidation film is formed on side walls of the stepped sections.
The manufacturing processes in connection with such publications, however, were complex and poor in fabricating the notched parts of the gate film with a satisfactory thickness.
Thus, there are demands for a semiconductor device having a configuration that a notched part is not caused in the gate film on the open ends of the trenches.
In view of the circumstances described above, an object of the invention is to provide a semiconductor device which has a film with a uniform thickness even on the open ends of trenches without causing a notched part by using materials having a different oxidation rate, and a fabrication method thereof.
Another object of the invention is to provide a semiconductor device having trenches with more reliable open ends by filling impurities into a material having a fast oxidation rate among other material having a different oxidation rate in order to further differentiate its oxidation rate from the other materials and a fabrication method thereof.
SUMMARY OF THE INVENTION
A semiconductor device of the present invention comprises a semiconductor substrate; a dispersion layer formed on the semiconductor substrate; an insulation film formed on the dispersion layer; a layer which is formed on the insulation film and has an oxidation rate faster than the semiconductor substrate and the dispersion layer; trenches formed to pierce in the semiconductor substrate, the dispersion layer, the insulation film and the layer having a fast oxidation rate; and an oxidation film formed to cover the trenches, wherein the trenches have their open ends covered with an oxidation film which is formed by oxidizing the layer having the fast oxidation rate.
A method for fabricating a semiconductor device according to the present invention comprises the steps of forming a dispersion layer on a semiconductor substrate; forming an insulation film on the dispersion layer; forming on the insulation film a layer having an oxidation rate faster than the semiconductor substrate and the dispersion layer; forming trenches to pierce in the semiconductor substrate, the dispersion layer, the insulation film and the layer having a fast oxidation rate; forming an oxidation film on the trenches and concurrently forming an oxidation film covering open ends of the trenches by oxidizing the layer having the fast oxidation rate; and forming an electrode on the both oxidation films.
According to the present invention, the layer having the fast oxidation rate is substantially made of polysilicon and impurities may be added to the polysilicon. Moreover, according to the present invention, the layer having the fast oxidation rate has typically a thickness of not less than 100 nm, although the thickness changes depending on the thickness of the gate oxidation film.
Another method for fabricating a semiconductor device, comprises the steps of forming a polysilicon layer on a first region of a semiconductor substrate; adding impurities to the first region where the polysilicon layer is formed and a second region on the semiconductor substrate to form a dispersion layer on the second region; forming an insulation film on the polysilicon layer and the dispersion layer; forming trenches to pierce in the semiconductor substrate, the polysilicon layer, the dispersion layer and the insulation film; concurrently oxidizing the polysilicon layer and the trenches to form an oxidation film covering open ends of the trenches; and forming an electrode on the both oxidation films.
In the semiconductor device and the fabrication method thereof according to the invention, the dispersion layer comprises a base layer and a source layer.
A

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