Method of etching self-aligned vias to metal using a silicon...

Details Method of etching self-aligned vias to metal using a silicon... Method of etching self-aligned vias to metal using a silicon...

1999-12-28

2001-09-11

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S638000, C438S639000

Reexamination Certificate

active

06287952

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of manufacturing semiconductor integrated circuit interconnect structures. The invention relates more particularly to a method for etching self-aligned vias to metal using a silicon nitride spacer.
2. Background of the Invention
Semiconductor integrated circuit devices typically comprise silicon and multiple layers of vertically stacked metal interconnect layers with dielectric materials disposed between them. The fabrication of such devices typically involves the repeated deposition or growth, patterning, and etching of thin films of semiconductor, metal, and dielectric materials.
Semiconductor devices generally include two or more metal layers separated and insulated by one or more dielectric layers. Typically, electrical communication is established between a plurality of locations on the metal layers.
To make contact between layers, a contact opening or via is formed in the dielectric layer above a first metal layer. Vias and contacts are generally formed by photolithography. A photoresist is deposited over the dielectric layer and patterned by transmitting radiation through a mask onto the resist. The resist is then developed creating patterning areas resistant to etching. Exposed areas of the underlying dielectric material are then etched. Areas etched through to the first metal layer form vias to the first metal layer.
Semiconductor integrated circuit devices have become more complex over the years. To prevent the devices from growing larger, the features that make up the devices have gotten smaller. With smaller feature sizes, it is more difficult to align one feature relative to another and to control size tolerance as a function of nominal feature size. To overcome this difficulty, manufacturers have incorporated self-alignment features. Self-alignment is a technique in which multiple levels of regions on a wafer are formed using a single mask, thereby eliminating alignment tolerances required by additional masks.
For certain applications, dielectric material, or a laser ablative etch resistant coating, is removed, or ablated, from the sides of metal lines, for example, to enable access to the metal for programming. Overlay alignment errors of the dielectric material may result in loss of chip space for programming.
Currently, a via photoresist is patterned with optical steppers and etched with a timed oxide etch. The alignment of the photoresist for these vias is therefore critical and not easily achieved with current stepper technology. Additionally, due to the variability of the ILD thickness and any alignment errors, the via etch must be timed accurately.
To overcome alignment difficulties, some manufacturers use a conductive landing pad in a metal line of the first metal layer. The conductive pad reduces the chances of short circuiting the second metal because it is wider than the minium metal line width to provide additional alignment tolerance. However, a landing pad increases the width of a portion of a metal line and limits contacted metal line density. Metal lines typically must be separated by a minium threshold distance in order to lithographically define and etch the space between adjacent metal lines and to prevent excessive capacitive coupling between adjacent lines.
Another self-alignment method is known, which includes forming a via out of part of a first spacer made of a first dielectric and surrounded by a second dielectric in a first sandwich structure; forming a second sandwich structure disposed on the first sandwich structure and having a second spacer of the first dielectric that is surrounded by a second insulating layer; removing the second spacer and a portion of the first spacer to form a first opening; and forming a conductive layer in the first opening to create an integrated structure. This integrated structure is subsequently filled with a conductive material and does not allow for further etching.
Conventional alignment methods may lead to nonuniform openings adjacent to metal lines and inadequate or varied via depth. Therefore, there is a need for an etching process that provides satisfactory uniform openings and adequate via depth control; and thereby overcomes alignment problems.
SUMMARY OF THE INVENTION
The invention is a method of manufacturing an integrated circuit including the steps of: (1) providing a first inter-level dielectric layer having metal lines formed thereon; (2) depositing a silicon nitride layer over the metal lines and the first inter-level dielectric layer; (3) depositing a second interlevel dielectric layer on the silicon nitride layer; (4) depositing a photoresist on the second inter-level dielectric layer; (5) patterning vias on the second inter-level dielectric layer; (6) non-selectively oxide etching the second inter-level dielectric layer and the silicon nitride layer to form the vias; and (7) selectively nitride-to-oxide etching the silicon nitride layer to remove the silicon nitride layer surrounding the metal lines, wherein the etching stops at the first inter-level dielectric layer, thereby forming an access window.
Another aspect of the invention is a semiconductor including a first inter-level dielectric layer having metal lines and portions of a silicon nitride layer formed thereon; portions of a second interlevel dielectric layer formed on the portions of the silicon nitride layer; vias patterned with a photoresist on the portions of the second inter-level dielectric layer; and openings within the vias to a top and sides of the metal lines, forming an access window.


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