Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-04-14
2001-03-27
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06209121
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method and a system for improving a delay error. More specifically, the invention relates to a method and a system for improving a delay error due to circuit layout of a LSI or a printed circuit board, such as a digital logic circuit or the like.
2. Description of the Related Art
Conventionally, a method and a system for improving a delay error of this kind has been used for improving a delay performance of a path which does not satisfy a delay restriction in a layout of an LSI or a printing circuit board.
As prior art, reference is made to Japanese Unexamined Patent Publication (Kokai) Heisei 6-140514; Sho ISHIOKA, Masami MURAKATA, Masako MUROBUSHI, “Experiments and Evaluation of Timing Updating ECO”, 6-85, 6-88 (Paper No. 7K-8), Information Processing Society of Japan, No. 45 (latter-half year of 1992), Paper in National Meeting; “Performance-Oriented Synthesis of Large-Scale” (IEEE Transactions on Computer-Aided Design, Vol. CAD-6, No. 5, September, 1987, for example.
In the conventional system, a method for improving delay performance of the critical path is that a delay value is calculated on the basis of a virtual wiring length (length of not fixed wiring but temporarily determined wiring) or an actual wiring length (wiring fixed the path) after wiring process, a critical path (the path which does not satisfy a demanded value or the path close to the demanded value) is extracted, a circuit cell (hereinafter simply referred to as “cell”) presenting on the critical path is replaced with a different cell having the same function and a different delay performance, a logical connection information is modified, and subsequently arrangement and wiring process is re-done.
On the other hand, if the delay performance cannot be satisfied merely by replacing with the cell for too large delay, solution has been taken to go back to architecture design for improving delay performance.
In the conventional method as set forth above, even when the delay performance may be improved merely by replacing the cell, it is possible that the delay performance cannot be improved satisfactorily.
This is because that after changing the cell to that having different delay performance, all of the layout and wiring process is re-done from the beginning, and there is no guarantee that the layout position and wiring length are the same as that before changing the cell.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a method and a system for certainly improving delay performance by permitting maintaining of the layout position and wiring path after once layout and wiring are done.
According to one aspect of the present invention, a delay error improving method comprises the steps of:
performing delay analysis using an actual wiring information after wiring process;
extracting an objective cell for replacement on the basis of delay analysis;
replacing the objective cell with a delay improving cell;
resolving overlap of cells caused by cell replacement; and
performing re-wiring for the delay improving cell and the cell to be the object of overlap resolving.
Preferably, the step of resolving overlap may comprise the steps of
removing the wiring of the objective cell for replacement and the cell to be the object of overlap resolving; and
moving the cell to be the object of overlap resolving.
When moving of the cell to be the object of the overlap resolving to adjacent channel is caused, the step of resolving overlap may comprises the steps of:
removing the wiring of the objective cell for replacement and the cell to be the object of overlap resolving;
moving the cell to be the object of overlap resolving to adjacent channel; and
adding the virtual terminal on the channel boundary line to which the wiring of the moved cell is connected.
The delay error improving method may further comprise the steps of, after the step of performing rewiring,
performing re-calculation of a path delay with respect to the pass on which the replaced cell is present; and
performing display of signal path and a delay value when the calculated delay of the path with within a delay restriction value.
A delay error improving method may further comprise the steps of, after the step of re-wiring, performing a path delay with respect to the path on which the replaced cell is present, and
further performing replacement of other cell in the same path when the path delay still exceeds a delay restriction value.
When the path delay still exceeds a delay restriction value and other cell is not present in the same path, a display of improvement incompleteness may be performed.
According another aspect of the invention, a delay error improving system comprises:
a delay analyzing portion performing delay analysis using an actual wiring information after wiring process;
a cell extracting portion extracting an objective cell for replacement on the basis of delay analysis;
a cell replacing portion replacing the objective cell with a delay improving cell;
an overlap resolving portion resolving overlap of cells caused by cell replacement; and
a re-wiring portion performing re-wiring for the delay improving cell and the cell to be the object of overlap resolving.
The resolving overlap may comprises:
a wiring removing portion removing the wiring of the objective cell for replacement and the cell to be the object of overlap resolving; and
a cell moving portion moving the cell to be the object of overlap resolving.
The resolving overlap portion may comprise:
a wiring removing portion removing the wiring of the objective cell for replacement and the cell to be the object of overlap resolving when moving of the cell to be the object of the overlap resolving to adjacent channel is caused,;
a cell moving portion moving the cell to be the object of overlap resolving to adjacent channel; and
a virtual terminal adding portion adding the virtual terminal on the channel boundary line to which the wiring of the moved cell is connected.
The delay error improving system may further comprises,
a path delay re-calculating portion performing re-calculation of a path delay with respect to the pass on which the replaced cell is present after completion of process in the re-wiring portion after completion of process of the re-wiring portion; and
an improved path displaying portion performing display of signal path and a delay value when the calculated delay of the path with within a delay restriction value.
The delay error improving system may further comprise a cell re-replacement portion further performing replacement of other cell in the same path when the path delay still exceeds a delay restriction value, when the path delay exceeds a delay restricting value. The delay error improving system may further comprise an improvement incompleteness displaying portion displaying of improvement incompleteness when the path delay still exceeds a delay restriction value and other cell is not present in the same path.
REFERENCES:
patent: 5397749 (1995-03-01), Igarashi
patent: 5801958 (1998-09-01), Dangolo
patent: 5801960 (1998-09-01), Takano
patent: 5889677 (1999-03-01), Yasuda
patent: 1-173168 (1989-07-01), None
patent: 7-14927 (1995-01-01), None
Giovanni De Micheli, “Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits”,IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 5, Sep. 1987, pp. 751-765.
Do Thuan
NEC Corporation
Smith Matthew
Sughrue Mion Zinn Macpeak & Seas, PLLC
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