Logic circuit analysis system for deleting pseudo error

Details Logic circuit analysis system for deleting pseudo error Logic circuit analysis system for deleting pseudo error

1998-03-10

2001-05-15

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06233720

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a system which analyzes a logic circuit based on designations input by users, in order to exclude pseudo errors, more particularly to a logic circuit analysis system for confirming the correctness of the designations.
In a design step of the logic circuit, a delay analysis is performed in order to confirm whether a delay time of a signal path in the designed logic circuit satisfies design requirements.
Referring to
FIG. 9
, a conventional delay analysis system comprises a circuit information memory
1
, an analyzer
200
, and a result memory
3
. The circuit information memory
1
stores information which defines a circuit configuration of an analysis target. The analyzer
200
performs the delay analysis depending on the circuit information stored in the circuit information memory
1
. Moreover, the analyzer
200
includes a path extractor
201
and a delay time calculator
202
. The path extractor
201
obtains a path in a depth direction according to a Depth First Search method (hereinafter, referred to as a DFS method). The delay time calculator
202
computes a delay time of each path. The computation results are stored in the result memory
3
together with information of each path.
From the analysis results stored in the result memory
3
, paths that do not satisfy design requirements are found, that is, erroneous paths are found.
In order to extract a path automatically according to the DFS method, from among the paths to be extracted, logically meaningless paths (e.g., redundancy paths) may be included in the path extractor
201
. For example, in the circuit shown in
FIG. 10
, when a level of a pin-c is at “0”, a pin-a is selected, whereby the path expressed by “pin-a→selector →circuit→pin-d” is allowed to be effective. On the contrary, when a level of the pin-c is “1”, a pin-b is selected, and the path expressed by “pin-b→selector→circuit→pin-d” is allowed to be effective. However, in the circuit shown in
FIG. 10
, the pin-c is clamped to the level of “0” so that the circuit of
FIG. 10
always functions as the path expressed by “pin-a→selector→circuit→pin-d”. Therefore, in the circuits of
FIG. 10
, the following three paths exist physically.
path-X: “pin-a→selector→circuit→pin-d”
path-Y: “pin-b→selector→circuit→pin-d”
path-Z: “pin-c→selector→circuit→pin-d”
However, since the path-Y makes no operation and the path-Z makes no signal change, these paths-Y and Z will be meaningless logically, that is, they will be redundant paths.
In the conventional system, the result memory
3
stores the information of each path as well as the delay time of the foregoing redundant paths computed by the delay time calculator
202
. Therefore, the analysis results for the logically meaningful paths and those for the redundant paths are mixed in the result memory
3
, so that judgment operations of the analysis results will be difficult.
Moreover, when paths unsatisfying design requirements of the previously decided delay time are extracted as erroneous paths, the redundant paths unsatisfying design requirements also are displayed as the erroneous paths. Such erroneous paths are called a pseudo erroneous path because they are essentially not an erroneous path.
In order to delete the erroneous paths, after the path extraction and the delay computation, the pseudo erroneous paths have been deleted from the analysis results according to the information of previously designated pseudo erroneous paths.
However, there may be mistakes about the designations for deleting the pseudo erroneous paths. Therefore, when essentially erroneous paths are erroneously designated as the pseudo erroneous path, in spite of the existence of the erroneous paths, there is a possibility that all of the analysis results are erroneously judged as normal ones.
SUMMARY OF THE INVENTION
In view of the foregoing problem of the conventional system, an object of the present invention is to provide an analysis system for a logic circuit which is capable of verifying whether designations to delete pseudo erroneous paths are correct.
In a circuit analysis system according to a first aspect of the present invention, a verifier verifies whether a designation of a path to be excluded from paths included in circuit information is correct. An analyzer extracts paths from said circuit information, and selects paths by deleting the designated path verified by said verifier from the extracted paths, thereby computing a delay time for each of the selected paths.


REFERENCES:
patent: 5815655 (1998-09-01), Koshiyama
patent: 6-295324 (1994-10-01), None
patent: 7-249060 (1995-09-01), None
patent: 8-147344 (1996-06-01), None

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