Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
1997-09-11
2001-03-27
Banankhah, Majid (Department: 2755)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S243000, C712S225000, C712S228000
Reexamination Certificate
active
06209085
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of computers, particularly to the area of process switching in multiprocessor computer systems.
2. Description of the Related Art
A processor comprises a number of registers contained in its register set for use during the execution of a process. The contents of these registers at any given time during the execution of a process is referred to as the “register state” of that process. Through the use of an operating system, many processors are capable of multitasking several processes using techniques such as cooperative multitasking, time-slice multitasking, etc. While multitasking several processes, a process's register state must be preserved (i.e., stored in a storage device) during the execution of other processes so that the process's register state may be loaded back into the processor and execution of that process may be resumed. When a processor switches from one process to another, a process switch (also termed as a “context switch” or a “task switch”) is said to have occurred.
Today, certain computer systems have more than one processor. Such computer systems are commonly referred to as multiprocessor computer systems. In many multiprocessor systems, a processor cannot access the registers of the other processors in the system, but must communicate with the other processors through a common storage area. In addition, many multiprocessor systems allow processes to “migrate” between processors (i.e., a processor may resume the execution of a process which was partially executed on a different processor). To allow a process to migrate from a first processor to a second processor, its current register state must be stored in the common storage area so that the second processor may access it. For example, after a first processor partially executes a first process, it may perform a process switch to a different process. As a result, this partially executed first process will be idle. In a single processor computer system, this first process must remain idle until the first processor returns to it. However, in a multiprocessor computer system, if the first processor stores the current register state of the first process in the common storage area, a second processor may access the common storage area and resume processing the first process from the point where the first processor left off.
One method in the prior art for preserving register states requires, upon the occurrence of every process switch, the saving of the previous process's entire register state in a common storage device and the loading of the next processes entire register state. As a result, the current register state of a process is always stored in the common storage area and is always available to the other processors. One problem with this method is that it requires a significant amount of save/load overhead during each process switch because of the large number of registers in a processor. It is likely future processors will contain even more registers.
A second method in the prior art for preserving register states in a single processor system employs disable bits for certain “register files” (i.e., groupings of registers—e.g., the floating point registers may be grouped as the floating point register file). According to this second method, the contents of the floating point register file are not saved or loaded as part of a process's register state during process switches, but the floating point register file is assigned a disable bit. Initially, this disable bit is set to indicate the floating point register file is enabled. In response to a first process utilizing the floating point register file, the disable bit is set to indicate the floating point register file is disabled. During a process switch from the first process, only that portion of the register state of the first process which is not stored in the floating point register file is stored in a storage device. When and if a second process attempts to utilize the floating point register file, the contents of the floating point register file are saved in the storage device and that portion of the register state for the second process which corresponds to the floating point register file is loaded into the register file. However, if no other processes utilize the floating point register file while the first process is not executing, the floating point register file is not saved or loaded. In this manner, disable bits permit the operating system to delay, and possibly avoid, the saving and loading of the floating point register file. Thus, process switch overhead is reduced by reducing the number of registers which must be saved and loaded.
A problem with the second prior art method described above is that a portion of a process' register state may be resident only in the floating point register file of the original processor (i.e., the values in the floating point register file of the original processor are not copied into memory until, if ever, a subsequent process executing on the original processor attempts to utilize the original processor's floating point register file). If a portion of the processor's register state is resident only in the original processor, a different processor cannot access the process' current register state (i.e., a processor cannot access a different processor's registers) and, therefore, the process cannot migrate. As a result, this prior art method is difficult to implement in a multiprocessor computer system, and when implemented in a multiprocessor computer system does not allow process' to freely migrate.
SUMMARY OF THE INVENTION
A method for reducing the amount of data copied during process switches is provided. According to one aspect of the invention, in response to a processor performing a process switch to a process, a first write indication corresponding to the process is stored to indicate a first register file in the processor should not be saved. In response to the process causing the processor to write to the first register file, the first write indication is altered to indicate the first register file should be saved. In response to the processor performing a process switch from the process, a first value stored in the first register file is stored in a storage device accessible by the processor if the first write indication indicates the first register file should be saved.
According to another aspect of the present invention, in response to a processor performing a process switch to a process, it is determined whether the process is likely to cause the processor to touch a first register file contained in the processor. If it was determined the process is likely to cause the processor to touch the first register file, a first value stored in a storage device accessible by the processor is loaded into the fast register file. A first load indication is stored to indicate whether the first value was loaded in the preceding step. In response to the process attempting to cause the processor to touch the first register file while the first load indication indicates the first value is not loaded, the first value stored in the storage device is loaded into the first register file and the first load indication is altered to indicate the first value was loaded.
According to another aspect of the present invention, an apparatus for reducing the amount of data copied during process switches is provided. The apparatus generally includes processor comprising a first storage area and a second storage area. The second storage area storing therein a first indication indicating whether, since a process switch to a process currently executing on the processor, the process has instructed the processor to write to the first storage area. According to another aspect of the present invention, the processor further comprising an execution unit which, in response to the process instructing the processor to write to the first storage area, alters the first indication to indic
Hammond Gary N.
Yamada Koichi
Banankhah Majid
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
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