Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
1999-07-12
2001-05-15
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S051000
Reexamination Certificate
active
06233196
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit memory devices and more particularly to multi-bank integrated circuit memory devices having a plurality of banks of memory cells.
BACKGROUND OF THE INVENTION
Integrated circuit memory devices are widely used in consumer and commercial applications. As the operational speed of Central Processing Units (CPU) continues to increase, it also may be desirable to increase the operational speed of integrated circuit memory devices. Accordingly, synchronous Dynamic Random Access Memories (DRAM) have been developed that operate in synchronization with a system clock. Moreover, multi-bank integrated circuit memory devices also have been developed in which a plurality of banks of memory cells are provided. The plurality of banks of memory cells may operate in an interleaved manner to increase the operational speed of the multi-bank integrated circuit memory devices.
As the integration density of integrated circuit memory devices continues to increase and the operational speed increases, it is known to increase the number of banks to thereby increase the effective bandwidth of the multi-bank integrated circuit memory devices. For example, a 16-Mb DRAM may include two banks, a 64-Mb DRAM may include two or four banks, a 256-Mb DRAM may include four banks and other high-speed integrated circuit memory devices such as Rambus integrated circuit memory devices may include 16 or more banks.
Prefetch schemes also may be used in synchronous DRAMs to operate at high speeds. In particular, in a synchronous DRAM having a prefetch scheme, an external address or command may be input for every two cycles of the system clock. Moreover, at least two Column Select Lines (CSL) that are selected by at least two column addresses, may be enabled for two cycles of the system clock. This operation is often called a 2N rule or a 2-bit prefetch.
In multi-bank integrated circuit memory devices, the respective banks may include independent row decoders and column decoders that operate independently. When the number of banks increases and a prefetch scheme is used, the banks may be arranged in a plurality of rows and columns of banks. Each bank generally receives its own row address information so as to be independently controlled. Accordingly, as the number of banks increases, the number of row address signal lines may also increase and the size of the integrated circuit may also increase undesirably.
It is also known to divide each bank of memory cells into two sub-banks of memory cells that are arranged in a plurality of rows and columns of sub-banks of memory cells. For example, in a publication by Saeki et al., entitled “A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996, pages 1656-1665, a multi-bank integrated circuit memory device is described including four banks, each of which consists of two sub-banks for lower byte data and upper byte data. As illustrated in
FIG. 1
of the Saeki et al. publication, the sub-banks are arranged in two rows and four columns with the two sub-banks of each bank being in the same row. Unfortunately, as the number of banks continues to increase, the number of signal lines that transmit row address information also may continue to increase and the size of the multi-bank integrated circuit memory device also may increase undesirably.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved multi-bank integrated circuit memory devices.
It is another object of the present invention to provide improved multi-bank integrated circuit memory devices wherein a plurality of banks of memory cells are divided into sub-banks of memory cells that are arranged in a plurality of rows and columns of sub-banks of memory cells.
It is still another object of the present invention to provide multi-bank integrated circuit memory devices including sub-banks of memory cells, that need not unduly increase the size of the integrated circuit due to the large number of row address lines thereof.
These and other objects are provided according to the present invention by multi-bank integrated circuit memory devices that include a plurality of banks of memory cells that are divided into pairs of sub-banks of memory cells. The sub-banks of memory cells are arranged in a plurality of rows and columns of sub-banks of memory cells. The pairs of sub-banks extend diagonally relative to the plurality of rows and columns of sub-banks of memory cells. The pairs of sub-banks of the respective banks preferably are adjacent one another and extend diagonally relative to the plurality of rows and columns of sub-banks of memory cells. By providing diagonally extending sub-banks, the row address lines that extend between respective sub-banks of each bank may occupy reduced area. More specifically, the row address lines that extend between pairs of sub-banks in same adjacent rows and same adjacent columns can cross over one another to thereby allow reduced area.
Multi-bank integrated circuit memory devices according to the present invention comprise a plurality of banks of memory cells that are divided into sub-banks of memory cells that are arranged in a plurality of rows and columns of sub-banks of memory cells. The sub-banks of at least one bank are located in different rows and different columns of sub-banks of memory cells. The sub-banks of the at least one bank preferably are located in adjacent rows and adjacent columns of sub-banks of memory cells. More preferably, the sub-banks of each bank are located in different rows and different columns from one another and most preferably, the sub-banks of each bank are located in adjacent rows and adjacent columns relative to one another.
A row decoder may be provided between adjacent sub-banks of two banks in a row of sub-banks. A column decoder also may be provided between adjacent sub-banks of the two banks in a column of sub-banks. A peripheral circuit block also may be provided adjacent one of the adjacent sub-banks of the two banks in a column of sub-banks, and opposite the column decoder.
A plurality of row address lines extends between respective sub-banks of each bank in adjacent rows and adjacent columns. The row address lines that extend between two pairs of respective sub-banks in same adjacent rows and same adjacent columns preferably cross over one another. They preferably cross over one another along the diagonals between the two pairs of sub-banks of memory cells. Accordingly, the area of the integrated circuit that is occupied by the row address lines need not increase unduly as the number of banks increases.
REFERENCES:
patent: 5280447 (1994-01-01), Hazen
patent: 5636174 (1997-06-01), Rao
patent: 5978302 (1999-11-01), Merritt
patent: 7-161183 (1995-06-01), None
patent: 98-4968 (1998-03-01), None
Saeki et al., A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM With Synchronous Mirror Delay, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1656-1665.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Zarabian A.
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