Electronic digital logic circuitry – Multifunctional or programmable – Significant integrated structure – layout – or layout...
Reexamination Certificate
1999-09-21
2001-08-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Significant integrated structure, layout, or layout...
C326S082000, C326S105000
Reexamination Certificate
active
06278292
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated circuit having a first logic unit with an activation input and with two outputs, which are connected to a respective input of a second logic unit via a respective signal line. The first logic unit outputs a first potential level at both outputs in the deactivated state and a second potential level on at least one of the outputs in the activated state. The second logic unit has at least two outputs, at which it generates potential changes depending on potential changes at its inputs.
SUMMARY OF THE INVENTION
The invention is based on the object of specifying an integrated circuit of the aforementioned type in which level changes at a plurality of the outputs of its second logic unit, which are triggered by level changes at the inputs of the second logic unit, take place simultaneously even if the signal propagation times on the two signal lines between the outputs of the first logic unit and the inputs of the second logic unit differ from one another.
With these objects in view there is provided, in accordance with the invention, an integrated circuit, comprising:
a first logic unit having an activation input and two outputs;
a second logic unit having an activation input and having two inputs each connected to a respective one of the outputs of the first logic unit via a respective signal line;
the first logic unit outputting a first potential level at the two outputs in a deactivated state and a second potential level on at least one of the two outputs in an activated state thereof;
a delay unit having two inputs each connected to a respective one of the signal lines and an output connected to the activation input of the second logic unit;
the second logic unit having at least two outputs generating, upon being activated, a level change on account of a level change at one of the two inputs;
the delay unit deactivating the second logic unit via the output when the first potential level is present at the two inputs, and activating the second logic unit when the second potential level is present at one of the two inputs; and
the delay unit triggering a temporally delayed level change at the output on account of a level change at one of the inputs with a delay at least as long as a difference between respective signal propagation times on the two signal lines between the outputs of the first logic unit and the inputs of the second logic unit.
In accordance with a concomitant feature of the invention, each of the inputs of the delay unit is connected to a respective one of the signal lines at a point significantly nearer to the inputs of the second logic unit than to the outputs of the first logic unit. The spacing is easily maximized by placing the taps in vicinity to the inputs of the second logic unit, so that any propagation delay from the taps to the inputs is negligible or essentially non-existent. In this way, the circuit properly compensates for the differences in the propagation delay in the signal lines connecting the first and second logic units.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5724287 (1998-03-01), Takenaka
patent: 3711604A1 (1987-10-01), None
patent: 0 223 275 A1 (1987-05-01), None
patent: WO 92/09140 (1992-05-01), None
Patent Abstracts of Japan No. 06310999 (Yasuo), dated Nov. 4, 1994.
Patent Abstracts of Japan No. 4-213914(A) (Mori), dated Aug. 5, 1992.
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
Tokar Michael
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