Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1998-10-09

2001-08-07

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S226000

Reexamination Certificate

active

06272055

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a semiconductor memory device in which low level potential of sense amplifiers, memory cells and bit lines constituting a memory cell array is adapted to be higher than the low level of the word lines of the chip body, in a dynamic random access memory including a memory cell array arranged on a semiconductor substrate, sense amplifiers and circuitry for controlling these.
2. Description of the Background Art
FIG. 101
is a schematic diagram showing a main portion of a conventional DRAM. Referring to
FIG. 101
, a memory cell MC is connected to a word line WL and a bit line pair BL, {overscore (BL)}. Bit line pair BL and {overscore (BL)} is connected to an n channel sense amplifier
2
, an equalizer circuit
3
and a p channel sense amplifier
4
through transfer gates Tr
71
and Tr
72
. Transfer gates Tr
71
and Tr
72
are controlled by a gate control signal BLI. To equalizer circuit
3
, a VBL signal at the potential of ½Vcc as well as an EQ signal are applied. In response to the EQ signal, equalizer circuit
3
precharges bit lines BL and {overscore (BL)} to ½ Vcc by VBL signal. Sense amplifiers
2
and
4
are to amplify a small potential difference read from the memory cell MC to the bit line pair BL and {overscore (BL)}. Sense amplifier
2
is activated when a sense amplifier activating signal SO is applied to a sense drive line SN, while sense amplifier
4
is activated when an activating signal {overscore (SO)} is applied to a sense drive line SP.
FIG. 102
is a time chart showing the operation of the memory array shown in FIG.
101
. There are a plurality of blocks of the memory array shown in
FIG. 101
, and each block is activated when a corresponding block activating signal is applied thereto. However, at this time, sense amplifiers
2
and
4
have not yet been activated. When data is to be read from memory cell MC, the BLI signal attains to the “HI” level, transfer gates TR
71
and TR
72
are rendered conductive, and bit line pair BL, {overscore (BL)} is connected to sense amplifiers
2
and
4
and to equalizer circuit
3
. When word line WL rises to the boosted voltage vpp as shown in (a) of
FIG. 102
, a small potential difference is read from memory cell MC to bit line pair BL and {overscore (BL)}, activating signal SO attains to the “HH” level and activating signal {overscore (SO)} attains to the “L” level as shown in (b) and (c) of
FIG. 102
, and sense amplifiers
2
and
4
are activated, respectively. The small potential difference between the bit line pair BL and {overscore (BL)} is amplified by sense amplifiers
2
and
4
, and the potential is enhanced to the level of “H” or “L”.
Now, the “L” level of the amplitude of the bit line pair BL and {overscore (BL)} is the low level of the word lines. In this case, the “L” level of a non-selected word line is equivalent to the “L” level of the amplitude of the bit line pair BL and {overscore (BL)}. Therefore, because of sub threshold leak current of the word line which is at the low level of the word lines, charges stored in the memory cell MC flows to the bit line and the amount of charges decrease, resulting in possible destruction of the data in the memory cell MC. In order to prevent this phenomenon, conventionally, a negative voltage bias Vbb is applied to the memory array portion. However, it requires a negative potential generating circuit for generating the negative voltage bias Vbb. In addition, this approach has disadvantage such as increase of array noise as the current incidental to memory array operation flows to the side of the ground, floating of the “L” level of the non-selected word line, increase of the sub threshold leak current of the word line and degradation of the refresh characteristics.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor memory device in which threshold voltage of memory cell transistors can be set low and reliability can be improved, and in addition, which eliminates the need of a triple well structure.
Briefly stated, the semiconductor memory device of the present invention includes a memory cell array including memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines; a sense amplifier for amplifying a small potential difference read from the memory cell array to the bit line, a control circuit for controlling reading of data from the memory cell array and writing of data to the memory cell array, and a potential setting circuit for setting lines of low level potential in the sense amplifier, the memory cells and bit lines to a potential higher than the low level of the word lines.
Therefore, according to the present invention, since the lines of the low level potential of the sense amplifier group, the memory cells and the bit lines are set to a potential higher than the low level of the word lines, the threshold voltage of the memory cell transistor can be set lower, reliability can be improved, a boosted voltage generating circuit becomes unnecessary, and the triple well structure becomes unnecessary.
More preferably, in order to enhance the potential of the low level potential line by the threshold voltage of a semiconductor element, the potential setting circuit discharges the potential of the low level potential line by a second semiconductor element in response to a signal which corresponds to a period in which large current flows.
More preferably, the potential setting circuit includes a reference voltage generating circuit for generating a reference voltage which is approximately equal to the low level potential, and a potential compensating circuit for comparing the reference voltage with the low level potential line, and for compensating the potential of the low level potential line so that the potential becomes higher than the low level of the word lines. The potential compensating circuit includes a comparing circuit and a switching circuit which switches in response to the comparison output from the comparing circuit.
Further, potential setting circuit includes a sustain circuit for intermittently supplying a power supply potential to the low level potential line for compensating the potential thereof so that it attains a level higher than the low level of the word lines. The sustain circuit includes an oscillating circuit and a pumping circuit.
More preferably, the potential setting circuit includes a reference voltage generating circuit for generating a reference potential, a comparing circuit for comparing the reference voltage with the potential of the low level potential line, and a switching circuit for discharging the potential of the low level potential line to the low level of the word lines side in accordance with the output from the comparing circuit.
More preferably, a low level lowering preventing circuit such as a diode is provided for preventing lowering of the potential of the low level potential line from the potential higher than the low level of the word lines.
More preferably, a voltage comparison stopping circuit for disabling the voltage comparing circuit while a large current flows, and floating preventing circuit for preventing floating of the potential of the low level potential line by forcefully operating the switching circuit while the large current flows are provided.
Further, more preferably, the sense amplifier includes a switching element connected between the low level potential line and the ground for enhancing the potential of the low level potential line by the threshold voltage thereof. The switching element includes a switching circuit which is rendered conductive when an input potential becomes equal to or lower than the low level of the word lines for applying a negative potential to an input electrode of the switching element while a large current flows so as to make short the response time. The switching circuit applies the low level of

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