Ferroelectric memory

Details Ferroelectric memory Ferroelectric memory

2000-02-10

2001-03-06

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S203000, C365S207000, C365S210130

Reexamination Certificate

active

06198653

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric memory which stores information in accordance with a polarization state of a ferroelectric material interposed between electrodes of a capacitor.
A semiconductor memory using a ferroelectric material is a nonvolatile semiconductor memory storing and holding information in a polarization direction thereof. Conventional nonvolatile semiconductor memories using a ferroelectric material will be described below.
FIG. 4
shows the circuitry of a conventional semiconductor memory as disclosed in U.S. Pat. No. 4,873,664.
FIGS. 5A
,
5
B,
5
C,
5
D,
5
E,
5
F and
5
G show an operation timing of the conventional semiconductor memory of FIG.
4
.
FIG. 6
shows a hysteresis characteristic of a ferroelectric material used in a memory cell capacitor in the conventional semiconductor memory.
FIG. 7
shows a hysteresis characteristic of a ferroelectric material used in a dummy cell capacitor in the conventional semiconductor memory.
In the circuitry of the conventional semiconductor memory of
FIG. 4
, a bit line (BIT)
26
and a complementary bit line (/BIT)
28
are connected with a sense amplifier
30
. Memory cells
20
a
,
20
b
, and
20
c
and a dummy cell
46
are coupled to the bit line
26
. Memory cells
20
d
,
20
e
and a dummy cell
36
are coupled to the complementary bit line
28
. The memory cell
20
a
includes a MOS transistor
24
and a memory cell capacitor
22
. The memory cell capacitor
22
includes two spaced apart plates, or electrodes, with a ferroelectric material between them. In the MOS transistor, the gate is connected with a word line
32
, the drain is connected with the bit line
26
, and the source is connected with a first electrode of the memory cell capacitor
22
. A second electrode of the memory cell capacitor
22
is connected with a plate line
34
. Similarly, the dummy cell
36
has a MOS transistor
38
and a dummy cell capacitor
40
. The dummy cell capacitor
40
includes two spaced apart plates, or electrodes, with a ferroelectric material between them. The gate of the MOS transistor
38
is connected with a dummy word line
2
, the drain is connected with the complementary bit line
28
, and the source is connected with a first electrode of the dummy cell capacitor
40
. A second electrode of the dummy cell capacitor
40
is connected with a dummy cell plate line
44
. The sense amplifier
30
is activated by a sense signal SE.
The circuit operation of the circuit of the conventional nonvolatile semiconductor memory will be described below with reference to the operation timing shown in
FIGS. 5A-5G
, the hysteresis characteristic of the ferroelectric film of the memory cell capacitor shown in
FIG. 6
, and the hysteresis characteristic of the ferroelectric film of the dummy cell capacitor shown in FIG.
7
.
FIGS. 6 and 7
show the hysteresis curves of the ferroelectric film. The abscissa represents the electric filed applied to the capacitor, and the ordinate represents the electric charge (polarization) corresponding to an electric field applied. Even when the electric field applied is zero, a polarization remains, that is, there exists a remanent polarization, in the ferroelectric capacitor, as shown in
FIGS. 6 and 7
at points B, E, H, and K. The remanent polarization values are used to represent nonvolatile data to thereby achieve a nonvolatile semiconductor memory. When the data of the memory cell is “1”, the memory cell capacitor has a state at point B of
FIG. 6
, whereas when the data is “0”, the memory cell has a state at point E of FIG.
6
.
Suppose that an initial state of the dummy cell capacitor is represented by the state at point K of FIG.
7
. To read the data of the memory cell
20
a
, the logic voltages of the bit line
26
, complementary bit line
28
, word line
32
, dummy word line
42
, cell plate line
34
, and dummy cell plate line
44
are each set to “L” (ground voltage: GND) as an initial state. Thereafter, the bit line
26
and the complementary bit line
28
are each set to a floating state. The logic voltage of the sense signal SE is set to “L” (ground voltage: GND).
Then, as shown in
FIGS. 5A-5D
, the word line
32
, the dummy word line
42
, the cell plate line
34
, and the dummy cell plate line
44
are each set to a logic voltage “H”. The logic voltage “H” of each of the word line
32
and the dummy word line
42
is a voltage (Vpp) obtained by boosting a supply voltage. The logic voltage “H” of each of the cell plate line
34
and the dummy cell plate line
44
is the supply voltage (Vcc). By this setting, the MOS transistor
24
of the memory cell
20
a
and the MOS transistor
38
of the dummy cell
36
are turned on. Thus, an electric field is applied to the memory cell capacitor
22
and the dummy cell capacitor
40
. If the data of the memory cell
20
a
is “1” at this time, the memory cell
20
a
undergoes a state change from the state at point B of
FIG. 6
to the state at point D. The difference Q
1
between the electric charge at point B and the electric charge at point D is read as the voltage of the bit line
26
. At this time, the dummy cell
36
undergoes a state change from the state at point K of
FIG. 7
to the state at a point J. The difference Qd between the electric charge at point K and the electric charge at point J is read as the voltage of the complementary bit line
28
. Then, the sense signal SE is set to the logic voltage “H” (supply voltage: Vcc). Thereby, the sense amplifier
30
amplifies the difference between the voltage of the bit line
26
derived from the memory cell
20
a
and the voltage of the complementary bit line
28
derived from the dummy cell
36
. Then, the voltage of the bit line
26
is raised to the level of the supply voltage Vcc, and the voltage of the complementary bit line
28
is lowered to the level of the ground voltage GND, and data “1” of the memory cell
20
a
is read.
On the other hand, if the data stored in the memory cell
20
a
is “0”, the memory cell
20
a
undergoes a state change from the state at point E of
FIG. 7
to the state at point D. The difference Q
0
between the electric charge at point E and the electric charge at point D is read as the voltage of the bit line
26
. At the same time, the dummy cell
36
undergoes a state change from the state at point K of
FIG. 7
to the state at point J. The difference Qd between the electric charge at point K and the electric charge at point J is read as the voltage of the complementary bit line
28
. The sense amplifier
30
detects the difference between the voltage of the bit line
26
derived from the memory cell
20
a
and the voltage of the complementary bit line
28
derived from the dummy cell
36
. Then, the sense amplifier drops the voltage of the bit line
26
to the level of the ground voltage GND, raises the voltage of the complementary bit line
28
to the level of supply voltage Vcc, and reads the data “0” of the memory cell
20
a.
When the data of the memory cell
20
a
is “1”, the amplifying operation of the sense amplifier
30
causes both the bit line
26
and the cell plate line
34
to have the supply voltage Vcc. Thereby, no electric field is applied to the memory cell capacitor
22
, which then comes into the state at point E of FIG.
6
. Thereafter, to restore the memory cell capacitor
22
to its original state at point B of
FIG. 6
, the voltage of the cell plate line
34
is set to the ground voltage to change the memory cell capacitor
22
from the state at point E of
FIG. 6
to the state at point A, and then, the logic voltage of the word line
32
is set to “L”. As a result, no electric field is applied to the memory cell capacitor
22
. Thus, the memory cell capacitor
22
returns to the state at point B of FIG.
6
. Thereby, rewriting of the data “1” to the memory cell
20
a
is completed. Normally, a boosted or raised voltage (Vpp) is supplied to the word line
32
so that the “H” voltage of the bit line
26
is sufficiently applied to the memory cell capacitor
22
when it is pla

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