Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-06-30
2001-03-06
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S411000
Reexamination Certificate
active
06198138
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a MIS (metal-insulator-semiconductor) device (including MISFET (metal-insulator-semiconductor field-effect-transistor) and CCD (charge-coupled-device) structures), an analogue MISFET using MIS device, a threshold voltage correcting method using MIS device, a potential adjusting method using MIS device, a bias circuit using MIS device, a charge transfer device using MIS device, a solid-state imaging device using MIS device and a charge detecting apparatus using MIS device.
More particularly, this invention relates to a MIS device in which a threshold voltage or channel potential can be controlled in an analogue fashion.
This invention relates to a method of correcting a threshold voltage in which a fluctuation of a threshold voltage between MIS devices of a semiconductor integrated circuit composed of a plurality of MIS devices can be corrected.
This invention relates to a method of adjusting a channel potential in which a channel potential of a MIS device can be adjusted.
This invention relates to a bias circuit in which an output bias can be set in an analogue fashion.
This invention relates to a charge transfer device using a CCD.
This invention relates to a solid-state imaging device, such as a CCD solid-state imaging device and an amplifying-type solid-state imaging device.
This invention relates to a charge detecting device used in a solid-state imaging device.
CCD solid-state imaging devices have an imaging region composed of an n-type semiconductor substrate, a p-type well region formed on the n-type semiconductor substrate and a plurality of n-type photoelectric conversion portions, i.e., light-receiving portions formed on the p-type well region in a matrix fashion.
In the above CCD solid-state imaging device, an allowable amount of signal charges e accumulated in the light-receiving portion when light becomes incident on the light-receiving portion, i.e., an amount of signal charges treated by the light-receiving portion is determined by a height of a potential barrier &phgr;
a
of an overflow barrier OFB composed of the p-type well region as shown in potential distribution diagrams of
FIGS. 1A and 1B
. Specifically, if the signal charges e accumulated in the light-receiving portion exceeds the amount of signal charges treated by the light-receiving portion, then extra charges are overflowed through the potential barrier &phgr;
a
of the overflow barrier OFB and discharged to the n-type substrate forming an overflow drain OFD.
The amount of signal charges treated by the light-receiving portion, i.e., the height of the potential barrier &phgr;
a
of the overflow barrier OFB is controlled by a bias voltage applied to the n-type substrate forming the overflow drain OFD, i.e., so-called substrate voltage V
sub
. However, according to this device structure, since device structures are frequently fluctuated when they are manufactured, the height of the potential barrier &phgr;
a
of the overflow barrier OFB is frequently fluctuated as shown by a dotted line height &phgr;
a
, in FIG.
1
A. Therefore, each time devices are manufactured, different substrate voltages V
sub
, V
sub
′ have to be set, respectively.
In the CCD solid-state imaging device, as shown in
FIG. 2
, a floating diffusion region FD for converting electric charges into voltages is formed at the succeeding stage of a horizontal transfer register
1
through a horizontal output gate portion HOG. There are provided a reset gate portion
2
and a reset drain region
3
for resetting signal charges transferred to the floating diffusion region FD at every pixel.
The horizontal transfer register
1
is composed of an n-type transfer channel region
5
formed on the surface of the p-type well region
4
, for example, a gate insulating film and a plurality of transfer electrodes
6
[
6
A,
6
B]. The adjacent two transfer electrodes
6
A and
6
B are paired. Two-phase horizontal drive pulses &phgr;H
1
and &phgr;H
2
are applied to every pair of transfer electrodes
6
[
6
A,
6
B] and every other pair of transfer electrodes
6
[
6
A,
6
B]. A p-type region
7
, for example, is formed on the transfer channel region
5
under each second transfer electrode
6
B by implantation of ions thereby to form a transfer portion including a storage electrode formed of the first transfer electrode
6
A and a transfer portion formed of the second transfer electrode
6
B.
The horizontal output gate portion HOG is composed of the gate insulating film (not shown) and a gate electrode
8
formed thereon through the gate insulating film. A ground potential is applied to the gate electrode
8
. The floating diffusion region FD is formed of an n-type semiconductor region, for example, and connected to a charge detector
9
whose detected output signal is obtained at an output terminal t
1
. The reset drain region
3
is formed of an n-type semiconductor region, for example, and a reset voltage V
RD
, e.g., a power supply voltage V
DD
is applied to the reset drain region
3
.
The reset gate portion
2
is composed of the gate insulating film (not shown) and a gate electrode
10
formed thereon through the gate insulating film. A reset pulse &phgr;
RG
is applied to the gate electrode
10
.
In recent CCD solid-state imaging devices, a driver circuit for applying the drive pulses &phgr;H
1
, &phgr;H
2
is incorporated in the horizontal transfer register
1
and a driver circuit for applying the reset pulse &phgr;
RG
is incorporated in a timing generator. Moreover, in order to reduce a power consumption, an amplitude of a pulse is lowered.
Since an operation point of the reset pulse &phgr;
RG
is determined depending on the power supply voltage V
DD
which is the reset voltage V
RD
, there is then the problem that a potential under the reset gate portion
2
is fluctuated (shown by a dotted line in FIG.
2
). To solve this problem, a DC bias value of the reset pulse &phgr;
RG
has to be set to a desired value for every device. The DC bias value of the reset pulse &phgr;
RG
is set by an external circuit (i.e., so-called bias circuit). When the driver circuit for applying the reset pulse &phgr;
RG
is incorporated within the timing generator, the DC bias value of the reset pulse &phgr;
RG
is digitally set in a so-called phase-cut fashion.
Further, an amplifying type solid-state imaging device is known as a solid-state imaging device. The amplifying type solid-state imaging device accumulates photoelectrically-converted holes (signal charges) in a p-type well region of an n-channel MOS (metal-oxide-semiconductor) transistor and outputs a change of channel current based on a potential fluctuation (i.e., potential change in the back-gate) in the p-type well region as a pixel signal. An n-type well region is formed on a p-type substrate and the p-type well region in which signal charges are accumulated. This amplifying type solid-state imaging device also has to set a substrate voltage.
On the other hand, there is known an ultraviolet-light-erasure ROM (read-only memory) having a gate insulating film formed of an SiN film to memorize data by controlling a potential.
FIG. 3
shows an example of such ultraviolet-light-erasure ROM. As shown in
FIG. 3
, a p-type region
11
has an n-type source region
12
and an n-type drain region
13
formed on its surface. A gate electrode
17
made of polycrystalline silicon, for example, is formed between the n-type source region
12
and the n-type drain region
13
through a gate insulating film
16
composed of a silicon oxide film
14
and a silicon nitride film
15
. Electrons or holes are accumulated in the silicon nitride film
15
to achieve a memory effect. However, this ROM can be turned on and off in a digital fashion. Therefore, when the SiN layer and the gate electrode contact with each other, injected electric charges e′ tend to be leaked to the gate portion and a DC bias of this ROM cannot be controlled in an analogue fashion.
Although CCD solid-state imaging devices are products using
Prenty Mark V.
Sonnenschein Nath & Rosenthal
Sony Corporation
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