Semiconductor memory device having redundancy memory circuit

Details Semiconductor memory device having redundancy memory circuit Semiconductor memory device having redundancy memory circuit

2000-01-27

2001-03-20

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189020, C365S230020

Reexamination Certificate

active

06205065

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundancy memory circuit. The present invention also relates to a method of selling such semiconductor memory device.
BACKGROUND OF THE INVENTION
Up to now, there has been a technique for relieving a memory chip having a small number of defective bit cells by replacing these defective bit cells with spare memory cells. In such a technique, for example, as shown in
FIG. 23
, in order to relieve a defective cell
501
indicated by “x” in a memory body or a basic memory
500
, the whole word line
502
containing the defective cell is replaced with a redundancy word line
503
. In this technique, however, there has been a problem that, since the whole of one row in a memory chip is replaced, in case defective cells
501
and
504
exist dispersedly as shown for example in
FIG. 23
, it is impossible to efficiently utilize spare memory cells.
In contrast with such a technique as described above, there is a semiconductor memory device formed so as to avoid waste of spare memory cells by utilizing an associative memory (see FIG.
24
). When an associative memory
505
is used, a defective address and its data are stored in the associative memory
505
and the data portion is selected on the basis of the content of the address portion.
FIG. 25
is a block diagram showing an example of a general structure of a conventional semiconductor memory device which uses an associative memory as shown in
FIG. 24. A
semiconductor memory device
506
shown in
FIG. 25
uses a selector
507
and connects data selectively between an external data bus and a memory body
500
or a redundancy group
509
, in a memory group
508
, according to a result of referring to the address portion of the associative memory
505
based on the content of an external address bus. By the changeover of this selector
507
, it is possible to replace defective cells. A conventional semiconductor memory device using such an associative memory is disclosed, for example, in Japanese Patent Laid-Open Publication No. 62-250599 “Semiconductor Memory Device”, Japanese Patent Laid-Open Publication No. 4-263199 “Semiconductor-Integrated Memory”, and the like.
FIG. 26
is a block diagram showing an example of a structure of a portion for referring to the associative memory
505
shown in FIG.
25
. In the structure of
FIG. 26
, the address bits of a cell to be replaced are stored in memory cells A
0
(
600
), A
1
(
601
), . . . , A
29
(
629
) of an associative memory (corresponding to the address portion of FIG.
24
). Coincidence of the content of the associative memory with the address bits A
0
_ext, A
1
_ext, . . . , A
17
_ext inputted from the outside is judged in a plurality of EOR gates (exclusive OR gates)
520
,
520
, . . . . Further, coincidence or noncoincidence of all the bits is judged by receiving the outputs of those gates with a NOR gate
521
, and a coincidence detection signal (word line) is outputted. If both coincide, memory cells A
18
(
618
), . . . , A
29
(
629
), memory cell data
630
corresponding to the data portion of
FIG. 19
, and a memory cell flag
631
for storing flag data showing a usage state (whether or not the relevant entry is valid) of the memory cell data
630
are selected and the data of each memory cell is outputted to a bit line. Thus, changeover by the selector is performed by referring to data of these word line and bit lines.
As described above, in a conventional semiconductor device, replacement of a bit defect has been performed by using an associative memory. However, since an associative memory is composed of a combination of a logic gate portion and a memory cell portion, the attempt to increase the number of replaceable bit cells tends to make the circuit more complicated in structure and larger in scale. Therefore, particularly when the capacity of a spare memory cell group is to be enlarged, there occurs a problem in a measure of using an associative memory.
On the other hand, generally, in addition to being judged to be defective due to defective operation of a memory cell as described above, a semiconductor memory device may be judged to be defective due to a fact that it cannot meet required specifications because of deterioration in operating characteristic although it is not defective in operation. For example, there is deterioration in data retention characteristic (characteristic with respect to the magnitude of a data retention current) in a DRAM and the like. Since deterioration in data retention characteristic is caused by generation of a cell having a large leak current in bits, it is possible to relieve a semiconductor memory device that is defective in specifications by replacing a bit cell which is defective in data retention characteristic with a spare memory cell. On the other hand, in the prior art, for example, in case a DRAM having a good data retention characteristic (finally a DRAM having a small data retention current) is to be obtained by replacing each of bit cells defective in data retention characteristic, in order to use spare memory cells without waste, there was only a method using an associative memory as shown in FIG.
24
.
Since a conventional technique using an associative memory intended primarily to relieve a hardware error, it was enough to prepare an associative memory having small capacity. In order to improve the data retention (or data holding) characteristic, however, it is sometimes necessary to replace memory cells of about 0 to 1 percent of a basic memory with spare memory cells, and it was difficult to replace a great number of memory cells (about 0 to 1 percent) by using memory cells each having a large area like an associative memory for the purpose of improving the data retention characteristic.
As described above, in order to improve a data retention characteristic, it is necessary to relieve a large number of bit cells existing in a DRAM and the like. Up to now, however, with respect to the relief of a large number of bit cells, since there is a problem of the mounting area of an associative memory and in general there is a problem of quality in case a chip having a great number of defective bit cells is relieved, such a meaningless relief has not been performed. In other words, the reason is that it is conceivable that, since such a chip originally has poor quality, even if bit cells which are really defective due to defective operation are relieved, defects are liable to appear on portions other than relieved portions immediately after the chip is used in practice.
On the other hand, there is a demand for making longer a data retention time for use in a portable telephone and the like. In order to improve the data retention time, it is necessary to relieve a great number of bit cells. Also, since this relief is performed not to relieve a really defective bit cell but to relieve a bit cell having a short retention time (having a short data retention time), it is also meaningful to relieve a number of defective cells. That is to say, in order to relieve bit cells having short data retention time, it is also effective to replace a large number of bit cells.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention, to obviate disadvantages of the conventional semiconductor memory device and a memory system using the same.
It is another object of the present invention to provide a semiconductor memory device and a memory system using the same in which a larger number of memory cells can be efficiently replaced with spare memory cells.
It is still another object of the present invention to provide a semiconductor memory device and a memory system using the same in which a larger number of memory cells can be efficiently replaced with spare memory cells without using a complex circuit structure.
It is still another object of the present invention to provide a semiconductor memory device and a memory system using the same in which a larger number of mem

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