Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
1999-03-30
2001-08-28
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C714S786000, C714S788000
Reexamination Certificate
active
06282677
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to an interleaving apparatus designed to rearrange a string of bits received or to be transmitted for eliminating errors locally occurring in the bit string.
2. Related Art
Recently, mobile communications systems such as portable telephones are in widespread use. Wireless communications systems such as mobile communications systems may experience local errors or burst errors taken place in a bit string to be received or transmitted. In order to minimize a lack of any bits caused by the burst errors, rearrangement of the bit string or interleaving is used.
Typical interleaving apparatuses are designed to subject a bit string to coding such as convolutional coding and interleaving for error correction and produces a coded and interleaved bit string.
FIG. 7
shows an input bit string.
FIG. 8
shows an interleaved and coded bit string. The interleaving is such that, for instance, a bit “
1
”(not shown) is coded and interleaved to produce a bit “
1
a
” and a bit “
1
b
” (not shown). In order to perform this function, the conventional interleaving apparatuses, as shown in
FIG. 9
, include a convolutional coding circuit
100
, a bit storage circuit
200
, a control circuit
300
, and an order storage circuit
400
.
The convolutional coding circuit
100
includes a plurality of registers A
1
to A
9
for convolutional coding. The convolutional coding
100
performs an operation C
1
=A
1
+A
4
+A
5
+A
7
+A
9
and an operation C
2
=A
2
+A
3
+A
4
+A
6
+A
8
on, for example, the first bit “
1
” in a bit stream to produce a bit “
1
a
” and a bit “
1
b
”, respectively. Specifically, C
1
and C
2
are calculated using predetermined initial values as values of the registers A
1
to A
8
and the bit “
1
” as a value of the register A
9
. The convolutional coding circuit
100
outputs the bit “
1
a
” and the bit “
1
b
” from ports
110
and
120
, respectively. Similarly, the convolutional coding circuit
100
produces bits “
2
a
” and “
2
b
” from the second bit “
2
” following the first bit “
1
” and also produces bits “
288
a
” and “
288
b
” from the last bit “
288
”. In the following discussion, the bits “
1
a
”, “
1
b
”, . . . “
288
a
”, and “
288
b
” will be referred to as coded bits.
The bit storage circuit
200
stores therein the coded bits in the order in which they are outputted from the convolutional coding circuit
100
. The control circuit
300
rearranges the coded bits in the bit storage circuit
200
in the order
1000
stored in the order storage circuit
400
. The order
1000
, as shown in
FIG. 10
, represents rearrangement of the coded bits and identical with the order of bits in a coded and interleaved bit string. The control circuit
300
outputs the rearranged coded bits or the coded and interleaved bit string to an quadrature converter circuit (not shown).
However, the conventional interleaving apparatus needs to have storage locations for all bits in an input bit string in the bit storage circuit
200
for coding and interleaving the bit string. For example, when 288 bits are inputted, the bit storage circuit
200
needs to have 576 storage locations (=288×2). Usually, an interleaving apparatus designed to convolutinally code N input bits at a coding rate R requires storage locations of a number for storing N×R bits. However, portable telephones have usually a small space for mount of parts and circuits. Thus, addition of the coding and interleaving function to the portable telephones requires a decrease in storage location in the bit storage circuit
200
.
SUMMARY OF THE INVENTION
It is therefore a principal object of the present invention to avoid the disadvantages of the prior art.
According to one aspect of the invention, there is provided an interleaving apparatus wherein a first bit string including a plurality of first bits is inputted to output a second bit string including a plurality of second bits each of which corresponds to one of the first bits and which are arranged in order different from that of the first bits, comprising: (a) a bit storage circuit storing therein the plurality of first bits; (b) an order storage circuit storing therein the order of the plurality of second bits; (c) a coding circuit producing a group of the second bits corresponding to one first bit by coding at least one of the first bits; (d) a control circuit transferring the first bits required to produce one of the second bits from the bit storage circuit to the coding circuit for producing the plurality of second bits according to the order; and (e) a selecting circuit selecting one of the produced group of the second bits according to the order.
In the preferred mode of the invention, the coding circuit is an error correction coding circuit.
The error correction coding circuit is a convolutional coding circuit coding the first bit specified by the one of the first bits for producing the group of second bits. The control circuit transfers the specified first bit.
The coding circuit may be a cyclic convolutional coding circuit which uses the one of the first bits and a result of coding of at least one of the first bits located ahead of the one of the first bits in the first bit string for producing the group of second bits and which includes a result storage circuit storing therein the result. The control circuit transfers the first bits from the bit storage circuit to the coding circuit and also transfers the result from the result storage circuit to the coding circuit.
The coding circuit performs coding for finding the result prior to coding to produce the plurality of second bits.
The result storage circuit stores a result of coding some of the first bits located at a given interval away from each other.
REFERENCES:
patent: 3652998 (1972-03-01), Forney, Jr.
patent: 4677624 (1987-06-01), Betts et al.
patent: 4677626 (1987-06-01), Betts et al.
patent: 5719875 (1998-02-01), Wei
Frank Robert J.
Moise Emmanuel L.
OKI Electric Industry Co., Ltd.
Venable
Wood Allen
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