Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-08
2001-04-03
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000, C438S745000, C438S759000
Reexamination Certificate
active
06211086
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor manufacturing, and in particular to a method of avoiding CMP caused residue on wafer edge uncompleted field.
2. Description of the Prior Art
Manufacturing of semiconductor substrates encompasses hundreds of different process steps. The steps involve creating patterns, introducing dopants, and depositing films on a silicon substrate repetitively throughout the manufacturing process to form integrated structures. Because the various structures that are built on a substrate or a wafer are serial in nature, that is, that they are built one on top of another in a sequential manner, it becomes very important that each layer of structure is substantially defect free before the next one is placed thereon.
Defects are generally caused when an unwanted particulate matter unintentionally lands between features on a layer and “bridges” or connects them, and therefore, disables them by “shorting” under certain conditions; or when an unwanted particulate matter lands on a feature, and disables it by creating an unwanted “open” in the circuitry. The size of the particulates in relation to the size of the features play an important role in creating the defects. As the size of features in today's high density integrated circuit chips (IC) are getting miniaturized ever so incessantly, control over the size of contaminants introduced into the manufacturing line need also be scrutinized diligently if acceptable levels of yield are to be maintained. Thus, for submicron lithographic technologies where the wiring features or patterns are less than one micrometer, &mgr;, in width, the size of the invading particulate matter need be controlled to between about one fifth to one tenth of the width, or between about 0.1-0.25&mgr;. With chip sites of about 5 mm.times.5 mm on a wafer, or of an area of 25 mm
2
, the allowable defect density is about 0.02 pieces/mm
2
in order to achieve satisfactory levels of yield. For larger chip areas on the order of 100 mm
2
, the defect density must be below 0.003 pieces/mm
2
in order to achieve the same yield.
Defects can best be avoided if the sources of the contaminants or dust particles are eliminated. There are mainly two major sources for contaminants that are introduced into a manufacturing line: the first one is that which resides outside the work piece, namely the wafer, such as the ambient air surrounding the wafer, or fluids, such as chemicals, that are brought to the work piece for various processes that take place at the work-station. These contaminants that are external to the work piece and sometimes are known as “drop-ons”, can generally be kept away from the work-piece by proper use of filters, and other implements that are commonly available. The other source for particle contaminants is the work piece itself, and the contaminants generated from the work-piece is sometimes referred to as being “process-induced.” As work is being performed on the work-piece, the work-piece releases particulate matter, or dust, due to abrasion or breakage caused by excessive stresses imposed on certain parts of the work-piece. Further on, the uncompleted fields of wafer edge with higher altitude will cause a lot of particulate matter after chemical mechanical polishing (CMP).
A case in point is when a wafer, for example, has ups and downs topography. As expected, defect particles will stay in fovea region and near uncompleted field of wafer edge to kill yield. Moreover, topography will cause photo-defocus issue at the following layers.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for manufacturing semiconductor device that substantially avoids residue near uncompleted field.
It is another object of this invention to improve the CMP uniformity and avoid SiN residue near uncompleted field.
It is a further object of this invention to prevent from topography caused next layers photo-defocus.
It is still another object of this invention to increase the yield of manufacturing semiconductor device.
In one embodiment, a method for forming a semiconductor device with avoiding chemical mechanical polishing caused residue on uncompleted fields of wafer edge is disclosed, wherein a band is reserved between the semiconductor device and the uncompleted. The method comprises removing all conductive layers on said uncompleted fields and removing all silicon nitride layers on said uncompleted fields, thereby the height of said uncompleted fields will not higher than the height of said semiconductor device.
REFERENCES:
patent: 5330931 (1994-07-01), Emesh et al.
patent: 5573633 (1996-11-01), Gambino et al.
patent: 5854140 (1998-12-01), Jaso et al.
patent: 6110828 (2000-08-01), Guo et al.
patent: 6133158 (2000-10-01), Obeng et al.
Chern Horng-Nan
Lee Tzung-Han
Elms Richard
Lebentritt Michael S.
United Microelectronics Corp.
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