Method for forming interconnect using dual damascene

Details Method for forming interconnect using dual damascene Method for forming interconnect using dual damascene

1999-11-12

2001-01-30

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S687000

Reexamination Certificate

active

06180514

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates about a method for forming interconnect, more particularly using dual damascene for precisely controlling the shape and area of the interconnect.
2. Description of the Prior Art
Currently, demand for integrated circuit (I.C.) has rapidly increased due to widespread use of electronic equipment. In particular, the increasing popularity of some electronic equipment such as, for example, many kinds of computers are gradually increasing the demand for the large or very large semiconductor memories in this modern century and next coming twenty-one century. Therefore, the advanced manufacture technology for improvement fabrication of integrated circuit should be urgently need than before.
Normally, the size and performance of the power IC devices depends critically on a specific at a particular breakdown voltage of the output devices. Since the thickness of semiconductor is usually limited by technological constraints, higher breakdown voltages typically require more layers. However, since the device on resistance is proportional to the expitaxial layer resistivity, higher breakdown voltages have to generally be traded off for limited drive current capability.
Thus, there is a conventional method described as referring with
FIG. 1A
to
1
D, which are the method for forming inter-metal dielectric by using dual damascene for precisely controlling the shape and area of the interconnect. Then, The following description will explain the various steps of one conventional method for forming dual damascene structure by reference FIG.
1
.
In the manufacture of a conventional dual damascene structure, there a substrate
100
has a metal layer
120
formed therein as shown in FIG.
1
A. An inter-metal dielectric layer
130
and a stop layer
132
are subsequently deposited on the substrate
100
. This stop layer
132
is silicon nitride as a trench etching stop layer. Then, another inter-metal dielectric layer
134
is coated on the stop layer
132
. A via patterned photoresist layer
140
is formed. Then, an anisotropically etch is performed to etch through inter-metal dielectric layer
134
, stop layer
132
, and inter-metal dielectric layer
130
, as shown in FIG.
1
B. Another photoresist layer
142
having a trench line pattern is formed next. Referring to
FIG. 1C
, trench line pattern
152
is transferred into the inter-metal dielectric layer
134
and ceased at stop layer
132
. Then, the photoresist layer
142
is removed. A barrier layer
162
is deposited and a metal layer
160
, such as tungsten or copper, is subsequently deposited to fill the via hole and trench line, as shown in FIG.
1
D. Finally, the dual damascene structure is completed by using chemical mechanical polishing method to remove excess metal layer.
For 0.18 &mgr;m process and beyond, dual damascene process is a key technology to push design rule tightly, but it is difficult to control the process window especially in via and metal trench formation. Thus, good resolution of lithography (misalignment issue) and high selectivity of via etching is the key issue for back end interconnection.
Therefore, within the microelectronics industry, there is an ongoing trend toward miniaturization coupled with higher performance. The scaling of transistors toward smaller dimensions, higher speeds, and low power has resulted in an urgent need for low constant inter-level insulators. Low dielectric constant inter-level dielectrics have already been identified as being critical to the realization of high performance integrated circuits. Thus, there exists a need in the microelectronics industry for a thermally stable, non-corrosive low dielectric constant polymer with good solvent resistance, high glass transition temperature, good mechanical performance and good adhesive properties, particularly to copper.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming interconnect using dual damascene structure that substantially obtains larger lithography process window without etching stop layer, i.e., PR lithography can be well controlled.
It is therefore an objection of this invention that with high height of photoresist and low height of SOG Oxide, via/trench etching is not necessary; thus, plasma damage on low k dielectric layer is avoided.
It is another object of this invention that silicon nitride stop layer is not used because damascene structure can be formed by two steps photoresist lithography. It is still another object of this invention that no via overetch issue (two steps trench/via etching); thus, process window of alignment adjustment (AA) control is improved.
It is yet another object of this invention that combination with low-dielectric constant layer, this process is very compatible with sub-0.18 &mgr;m technology.
In the embodiment, the method for forming interconnect, normally concludes the following steps. First of all, a semiconductor wafer is provided. Then, forming a first metal layer on a portion of the substrate is carried out. A first dielectric layer is formed on the first metal layer and the substrate. Consequentially a tantalum nitride layer is formed on the first dielectric layer. A first photoresist layer can be formed on the tantalum nitride layer, especially first photoresist layer has a first pattern defining a trench area located over the first metal layer, and has a second pattern defining an etch stop area. The tantalum nitride layer will be etched by the first photoresist layer. A second dielectric layer is formed over the etched tantalum nitride layer and the first dielectric layer. The second photoresist layer can be formed on the second dielectric layer, sepecially the second photoresist layer has a first pattern substantially aligned with the first pattern of the first photoresist layer, and has a second pattern substantially aligned with the second pattern of the first photoresist layer. Next, etching the second dielectric layer by the second photoresist layer can be achieved, portion of the first dielectric layer over the first metal layer is further etched by the first pattern of the first photoresist layer. Thus trenches are formed in the first dielectric layer and the second dielectric layer. Then the tantalum nitride layer is deposited into the trenches, especially barrier layer is formed on top surface of the trenches. A seed layer is formed on sidewalls of the etched first dielectric layer and the second dielectric layer. Sequentially, the trenches are filled by a second metal layer. Finally, the second metal layer is planarized to expose surface of said second dielectric layer.


REFERENCES:
patent: 6001733 (1999-12-01), Huang
patent: 6040243 (2000-03-01), Li et al.

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