Integrated circuit package and integrated circuit package...

Details Integrated circuit package and integrated circuit package... Integrated circuit package and integrated circuit package...

1998-06-10

2001-04-10

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S723000, C257S724000, C257S686000

Reexamination Certificate

active

06215192

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit package disposed on a bus formed on a printed board, and a system including such an integrated circuit package.
2. Description of the Related Art
With the recent improvement in the speed of data transfer between LSIs (large scale integrated circuits), problems such as (1) skewing between data and clocks and (2) disturbance of transfer data and a clock waveform due to noise and the like arise. In order to solve these problems, it is necessary to make uniform and short the lengths of buses running on a printed board between a controller and an LSI which exchanges data with the controller, i.e., the distances between the controller and the LSI. The “distance” as used herein refers to the length of a signal path.
At high-speed data transfer, in order to avoid the above problems, the distances from connection pads (hereinbelow, simply referred to as “pads”) to lead pins (hereinbelow, simply referred to as “pins”) via bonding wires (hereinbelow, simply referred to as “wires”) are required to be equal to one another due to the following reasons.
FIGS. 16A and 16B
exemplify timings at data transmission and data receiving, respectively, in the data transfer between LSIs disposed on a bus formed on a printed board. In this example, it is assumed that a transmitter LSI transmits data D
1
and D
2
at a timing T
1
(FIG.
16
A), and a receiver LSI receives the data D
1
and D
2
at a timing T
2
(FIG.
16
B).
The transmitted data D
1
and D
2
are transferred to the receiver LSI via corresponding pads, wires, and pins in the LSI package, as well as via the buses on the printed board. At this data transfer, if the lengths of the signal paths for these data are different from each other, the arrival times of the data are different from each other. If the difference in the data arrival time is equal to or exceeds a half of a clock period T, i.e., T/2, then data D
1
and D
2
are no longer received simultaneously at the timing T
2
. As a result, simultaneous time transfer of a plurality of data is not possible.
For the high-speed data transfer between LSIs, it is desirable to increase a clock frequency, which determines the timings of data receiving and data transmission. As the clock frequency becomes higher, the clock period T shown in
FIGS. 16A and 16B
becomes shorter. As a result, the difference in the data arrival time due to the different lengths of the signal paths described above becomes a serious problem. Accordingly, in order to realize high-speed data transfer, it is necessary to provide signal paths with equal lengths for respective data. The lengths of the pins and wires should also be made equal to one another.
A technique for solving the above problems is disclosed in U.S. Pat. No. 5,408,129, where, as shown in
FIG. 17
, equal distances from pins to corresponding pads formed on an integrated circuit board are realized by extending the pins only from one side of a package.
It is also required to reduce the length of each bus running from a controller on a printed board as described above. In order to avoid the above-described problems, the bus length should not exceed a predetermined limit. An integrated circuit should therefore be disposed on the bus within the predetermined bus length limit.
However, such a package that has pins extending only from one side thereof produces dead spaces as shown in FIG.
18
.
FIG. 18
is a plan view schematically showing surface horizontal packages (SHP) disposed on a bus. The dead space as used herein refers to an area obtained by excluding an area corresponding to a length d
1
or d
2
of a function block on an integrated circuit chip in the bus direction from the area occupied by the integrated circuit package. The area corresponding to the length d
1
of the function block in the bus direction refers to an area Sd
1
shown by sinking slanted lines in FIG.
18
. Hereinbelow, an area corresponding to a given length in the bus direction refers to an area having the same relationship therewith as that between the length d
1
and the area Sd
1
. For example, the area corresponding to a length a
1
in the bus direction is an area Sa
1
shown by rising slanted lines in FIG.
18
.
In
FIG. 18
, the areas corresponding to lengths a
1
, b
1
, c
1
, e
1
, a
2
, b
2
, c
2
constitute dead spaces. These dead spaces can be reduced, so that the bus length of the predetermined limit described above can be more effectively utilized.
SUMMARY OF THE INVENTION
The integrated circuit package of this invention includes a first integrated circuit chip and a second integrated circuit chip having a same function, wherein the first integrated circuit chip and the second integrated circuit chip are connected to a common bus.
In one embodiment of the invention, the first integrated circuit chip and the second integrated circuit chip are memory chips.
In another embodiment of the invention, the first integrated circuit chip and the second integrated circuit chip are disposed so that the first integrated circuit chip and the second integrated circuit chip are adjacent to each other in a plane.
In still another embodiment of the invention, the first integrated circuit chip and the second integrated circuit chip are disposed so that the first integrated circuit chip and the second integrated circuit chip overlap each other.
In still another embodiment of the invention, the first integrated circuit chip and the second integrated circuit chip are disposed so that one of the first integrated circuit chip and the second integrated circuit chip is placed face down with respect to the other.
In still another embodiment of the invention, the first integrated circuit chip includes a plurality of first pins connected to the common bus and a plurality of first pads connected to the plurality of first pins, and distances between points at which the first pins are connected to the common bus and the first pads to which the first pins are connected are substantially equal to one another.
According to another aspect of the invention, a system including an integrated circuit package and a control circuit for controlling the integrated circuit package is provided. In the system, the integrated circuit package includes a first integrated circuit chip and a second integrated circuit chip having a same function, and the first integrated circuit chip, the second integrated circuit chip, and the control circuit are connected to a common bus.
In one embodiment of the invention, the first integrated circuit chip and the second integrated circuit chip are memory chips.
In another embodiment of the invention, the first integrated circuit chip and the second integrated circuit chip are disposed so that the first integrated circuit chip and the second integrated circuit chip are adjacent to each other in a plane.
In still another embodiment of the invention, the first integrated circuit chip and the second integrated circuit chip are disposed so that the first integrated circuit chip and the second integrated circuit chip overlap each other.
In still another embodiment of the invention, the first integrated circuit chip and the second integrated circuit chip are disposed so that one of the first integrated circuit chip and the second integrated circuit chip is placed face down with respect to the other.
In still another embodiment of the invention, the first integrated circuit chip includes a plurality of first pins connected to the common bus and a plurality of first pads connected to the plurality of first pins, and distances between points at which the first pins are connected to the common bus and the first pads to which the first pins are connected are substantially equal to one another.
Thus, the invention described herein makes possible the advantages of (1) providing an integrated circuit package where integrated circuit chips can be disposed with a higher density within the range of a predetermined bus length limit, and (2) providing a system including such an integrated circu

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