Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-06-09
2001-09-04
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S185210
Reexamination Certificate
active
06285615
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to current mirrors and, more particularly, to multiple output current mirrors with improved accuracy.
2. Background Information
Current mirrors are a basic building block of many circuits and allow a given current flowing in one element to be replicated in another element. The accuracy of the mirror is determined by how closely the level of the original current, or a predetermined multiple of it, is reproduced. In a multiple output current mirror, more than one copy of the original current is provided as output.
One example of a prior art multiple output current mirror is shown in
FIG. 1
, where it finds application in the reading of a multi-level memory cell. In this arrangement, during a read operation a current I
cell
flows through the addressed cell
30
. The level of this current flow depends on which of (k+1) states the memory cell is in. To determine this state, the current is reproduced k times in current mirror
10
to produce currents I
1
, I
2
, . . . , I
k
One of a series of transistors
41
,
42
, . . . ,
49
is then placed to received the respective current, each being controlled by a respective reference value I
ref1
, I
ref2
, . . . , I
refk
, thereby acting as a series of reference circuits to sense the value of I
cell
relative to the I
ref
S. This allows the k currents I
i
; to be compared with the k reference levels, the result being determined by the k sense amps SAi. The circuit of
FIG. 1
is adapted from U.S. Pat. No. 5,172,338, which is hereby expressly incorporated herein by this reference, where it and a number of variations are described in more detail. The particular details of these peripheral portions of
FIG. 1
are not particularly important here except to provide a context for the multiple output current mirror
10
. The relevant property of current mirror
10
is that it provides accurate values of the currents I
1
-I
k
without degrading the original reference current, here I
cell
.
Current mirror
10
is a one-to-k arrangement, with a first transistor
20
on a first leg and a set of k second transistors
21
,
22
, . . . ,
29
on each branch of a second leg. When a current I
cell
flows in the first leg, the second transistor on each branch of the second leg behaves as a current source and supplies a reproduced current in its branch. The ratio of the reproduced currents to the original currents scales according to the relative sizes of the second transistors
21
,
22
, . . . ,
29
to the first transistor
20
. In
FIG. 1
, all of the transistors of current mirror
10
are shown with the same size, denoted by the symbol “X”. This results in a one-to-k current mirror in which the first current is reproduced in all the branches of the second leg, ideally with I
cell
=I
1
=I
2
= . . . =I
k
and without dilution of I
cell
. A more general set of current ratios can be set by the usual method of altering the relative width to length ratios of branches as described in more detail in the patent cited in the previous paragraph.
In practice, the results are less than ideal for a number of reasons. The above discussion assumes that all of the transistors can be manufactured to the desired dimensions and are independent of process variations. It also assumes that the transistors all function ideally, or at least function the same, independent of temperature gradients and other variations on the surface of the circuit that will give operating characteristics differing from the physical location of one transistor to the next. Additionally, it is assumed that the same voltage that is applied to the control gate of the mirrored transistor
20
is also applied to the control gate of each of the mirroring transistors
21
,
22
, . . . ,
29
with out any loss between, say, transistor
21
of the first branch and transistor
29
of the k-th branch. As the development of integrated circuits has progressed, design requirements, such as smaller size and lower operating voltages, have aggravated these problems.
As the response of a transistor depends upon the ratio of its width to its length, one way to improve accuracy is to increase its size in one or both dimensions so that the relative effect of a size variation in either dimension is minimized. Conversely, as device sizes have decreased, these relative dimensional variations result in larger device to device variations in device characteristics. In the application of
FIG. 1
, for example, it is common that the transistor size is determined by the pitch size of the memory cells. This effectively limits the width of the mirror transistors to the width of the group of transistors to be sensed together. In such an arrangement, the width of the mirror transistors could be increased by increasing the pitch size, but many factors go into deciding pitch size, with the width of the current mirror transistors only one, and often a lesser one, of these. The length of the transistors is not so restricted, but any increase in length leads to a larger die size and also results is any position dependent variations, either operational or process, being amplified.
With a multiple output current mirror, some of the transistors
20
-
29
are of necessity further from a given one than others, so that process variations result in less accurate mirroring as the number of legs increases. This physical separation also makes the multiple output current mirror more susceptible to temperature gradients and other variations in operating conditions on the circuit. Similarly, the further a given mirroring transistor is from the mirrored transistor, the more the voltages on their respective control gates will differ due to losses from the intervening transistors in other legs as well as other losses along the way.
As the operating voltages of devices become lower, the current levels have correspondingly decreased, so that the acceptable variations between the different mirroring I
i
S and the original mirrored reference current have become more critical. In the multi-level, non-volatile memory of the example, the ability to mass produce accurate memory chips depends crucially on a accurate current mirror to distinguish the states of the cells. This is also true of analog circuits where the relative variation in a replicated current needs to minimal. Therefore, an objective of the present invention is to provide a multiple output current mirror which is more accurate and less susceptible to the problems described above.
SUMMARY OF THE PRESENT INVENTION
The present invention presents a multiple output current mirror. A reference current is mirrored in number of branches to produce replicas of the original current without degrading the original current. Both the mirrored transistor, through which the original current flows, and the mirroring transistors, which provide the replicated currents in each of the branches, are subdivided into a number of separate transistors. The effective channel width of a corresponding original transistor is shared among the transistors forming its subdivision. These subdivided elements are then physically arranged into a number partial current mirrors whose outputs are combined to form the total current mirror. By altering the physical arrangement of the pieces from one partial mirror to the next, variations in operating characteristics and manufacturing processes that are dependent upon positions are reduced since the variation in one partial mirror offsets that in another partial mirror.
In one embodiment, the mirrored element, producing the reference current, and the mirroring elements in each of k branches are each composed of N transistors with a width w, giving an effective width W=Nw for each element and consequently a mirroring ration of
1
, for all the branches. All of these N(k+1) transistors are physical placed in a linear arrangement of N partial current mirrors of (k+1) transistors each, where each partial mirror contains a transistor supplying pa
Huynh Sharon Y.
Quader Khandker N.
Elms Richard
Phung Anh
SanDisk Corporation
Skjerven Morrill & MacPherson LLP
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