Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-01-26
2001-08-28
Cao, Phat Xuan (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S666000
Reexamination Certificate
active
06281570
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a tape carrier for BGA (Ball Grid Array) and a semiconductor device using the same, and more particularly to a tape carrier for BGA improved in wiring density and humidity resistance and to a semiconductor device using the same.
BACKGROUND OF THE INVENTION
Recently, in response to requirements for compactness of packages and high density of mounting packages, a package (semiconductor device) of a small size called CSP (chip size package) having BGA structure using a tape carrier facilitating high-density wiring has been proposed. Particularly, several kinds of packages equal in size to semiconductor chips have been developed. Among them, a micro-BGA package devised by TESSERA Company is noticed as a highly reliable semiconductor package.
Construction of majority of these semiconductor devices is of a style in which there is mounted a semiconductor chip of center-pad type, in which electrodes are formed to be arranged along the central line of the chip, on a silicon resin layer provided on one surface of a tape carrier having an opening. Electrode portions of the semiconductor chip, leads connected to solder balls formed on the tape carrier, and the opening of the tape carrier are embedded to be protected by insulative sealing material.
FIG.
1
and
FIG. 2
show the structure of wiring pattern in a conventional tape carrier having insulative film
7
having device hole
10
formed at the center and via-holes
11
, and plating power-feeding leads
13
to form gold electro-plating layer
14
on the wiring pattern of conductor layer
8
including leads
9
and lands
12
. Below tape carrier
2
, there is provided elastmer
3
for mounting a semiconductor chip. The outer ends of plating power-feeding leads
13
are cut off and removed by outside punching tools
17
or the like after gold electro-plating layer
14
is formed.
For the manufacture of the tape carrier, insulating film
7
made of polyimide or the like is punched to form device hole
10
and via-holes
11
, then, the wiring pattern of conductive layer
8
of leads
9
, lands
12
and power-feeding leads
13
are formed on insulating film
7
by way of photo-etching. Gold electro-plating layer
14
is provided on the wiring pattern, power-feeding leads
13
exposed outside is cut off and removed by means of outside punching tool
17
. Thereafter, elastic body (elastomer)
3
is provided on conductor layer
8
so as not to be projected outward from the periphery of insulating film
7
.
FIG. 3
shows the structure of a conventional semiconductor device of BGA type.
FIG. 4
shows a plan view of the semiconductor device (from the side of solder ball side).
FIG. 5
shows the bottom of the semiconductor device (semiconductor chip side).
The semiconductor device is provided with semiconductor chip
1
, tape carrier
2
, elastomer
3
fixing both of semiconductor chip
1
and tape carrier
2
, sealant
5
for protecting electrode portion
4
of semiconductor chip
1
, and solder ball
6
serving as electrode for the semiconductor device, in its structure.
Owing to the structure of this semiconductor device, semiconductor chip
1
is mounted and fixed on the side of elastomer
3
of the tape carrier, whereby electrode
4
of semiconductor chip
1
and lead
9
of the tape carrier are joined electrically. Further, electrode
4
of semiconductor chip
1
and lead
9
, thus joined, and device hole
10
are sealed air-tight by insulating sealant
5
. Then, solder ball
6
is placed on land
12
of the tape carrier, and at last, by cutting along piece-cutting line
21
(FIG.
2
), the semiconductor device is completed.
In the conventional tape carrier, however, wiring pattern is expanded and it is not easy to form a high density wiring, because the power-feeding leads
13
are drawn for each lead
9
. Thus, it is difficult to respond to requirements for compactness and increase in number of pins. Moreover, when a semiconductor device using a conventional tape carrier is subjected to PCT (pressure cooker test) to evaluate the humidity resistance after completion of the package, water permeates from the terminal surface of power lead
13
exposed to the outside of the package (
FIG. 3
) and reaches lead
9
connected to electrode portion
4
of the semiconductor chip, thereby corrosion occurs at electrode portion
4
of the semiconductor chip.
SUMMARY OF THE INVENTION
Accordingly, the object of the invention is to provide a tape carrier for BGA to be manufactured easily and capable of accomplishing higher density of wiring pattern, and to provide a semiconductor device using the same.
The other object of the invention is to provide a tape carrier for BGA improved in humidity resistance of wiring pattern of the tape carrier and reliability of the package, and a semiconductor device using the same.
According to the invention, a tape carrier for BGA including a predetermined pattern of lands for solder balls, leads connected to a semiconductor chip, and wirings for connecting the leads and the leads formed on an insulation film, the tape carrier, comprises:
a plating power-feeding lead formed on the insulative film, one end of the plating power-feeding lead being extended outside the insulative film, the other end of the plating power-feeding lead being connected to the leads or the wirings, and a predetermined point of the plating power-feeding lead at which an easily cutting portion is formed.
According to the other feature of the invention, a semiconductor device including a semiconductor chip having a plurality electrodes, and a tape carrier for BGA including a predetermined pattern of lands for solder falls, leads connected to the plurality of electrodes, and wirings for connecting the lands and the leads formed on an insulative film, the tape carrier, comprising;
a plating power-feeding lead formed on the insulative film, one end of the plating power-feeding lead being extended outside the insulative film, the other end of the plating power-feeding lead being connected to the leads or the wirings, and a predetermined point of the plating power-feeding lead at which an easily cutting portion is formed.
REFERENCES:
patent: 6114751 (2000-09-01), Kumakura et al.
patent: 2000-286294-A (2000-10-01), None
Kameyama Yasuharu
Okabe Norio
Cao Phat Xuan
Hitachi Cable Ltd.
Scully Scott Murphy & Presser
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