Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-27
2001-08-28
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S660000, C438S687000
Reexamination Certificate
active
06281110
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductors, and, in particular, to a method for making an integrated circuit including metal interconnect layers.
BACKGROUND OF THE INVENTION
A problem in the field of semiconductors is the degradation of device performance by hot carrier aging (HCA). This is a particular concern with respect to smaller devices in which proportionally larger voltages are used. When such high voltages are used, charge carriers can be sufficiently energetic to enter an insulating layer and degrade device behavior. Various approaches to addressing HCA are, however, expensive because they typically complicate the fabrication process.
After contact holes are patterned in a field oxide, a conductive metal layer is deposited (i.e. a metallization layer) to connect integrated circuit components. Metallization materials typically include aluminum and copper, for example. Copper is a better conductor than aluminum and because of reductions needed for 0.25 &mgr;m and sub 0.25 &mgr;m devices, copper is preferred as the metallization material. Additionally, copper is resistant to electromigration and can be deposited at low temperatures. A copper metallization layer may be formed by electrodeposition or electroplating. For a multi-metallization level device, after each step of electroplating copper, the device is annealed in a nitrogen gas atmosphere (forming gas) to stabilize the copper layer.
After the final metallization layer is formed, i.e. after the final copper electroplating step and the forming gas annealing step, a protective or passivation layer (cap) is formed on the device. Then, the device can be further annealed in a forming gas or deuterium gas atmosphere to reduce hot carrier aging. U.S. Pat. No. 5,872,387 to Lyding et al., for example, discloses a method for treating a semiconductor device which includes a step of passivating the device with deuterium. Thus, conventional techniques, e.g. as discussed above, necessitate relatively extended time annealing due to the numerous forming gas annealing steps during the electroplating of the copper metallization layers, in combination with the final annealing step after the device is substantially complete.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the invention to reduce the number of annealing steps and associated time needed to form an integrated circuit device having improved hot carrier aging and better operational characteristics.
It is a further object of the invention to reduce the number of annealing steps and associated time needed to form an integrated circuit device while providing microstructure stability of the metallization layers.
These and other objects, features and advantages in accordance with the present invention are provided by a method of making an integrated circuit including forming a plurality of copper interconnect layers adjacent a semiconductor substrate; and, annealing, in a deuterium ambient, each copper interconnect layer after formation thereof. The microstructure of the copper is thereby stabilized. The copper interconnect layers can be electrodeposited and the step of annealing each layer may be performed in a temperature range of about 400-450° C. Also, the deuterium ambient is preferably a deuterium enriched gas.
The method further preferably includes chemical-mechanical polishing (CMP) each copper interconnect layer after each copper interconnect layer is annealed. Inter-level dielectric layers are preferably formed between each of the plurality of copper interconnect layers and an overall passivation layer is formed over an uppermost copper interconnect layer. A last annealing step using deuterium is preferably performed prior to forming the overall passivation layer. In other words, an overall deuterium annealing is not required after the cap is formed.
Alternatively, the method may include forming a plurality of metal interconnect layers adjacent a semiconductor substrate, wherein at least one of the plurality of metal interconnect layers comprises copper. Then the at least one metal interconnect layer comprising copper is annealed in a deuterium ambient. In this embodiment, at least one of the plurality of metal interconnect layers may comprise another metal, such as aluminum, for example.
REFERENCES:
patent: 5872387 (1999-02-01), Lyding et al.
patent: 6023093 (2000-02-01), Gregor et al.
patent: 6071808 (2000-06-01), Merchant et al.
patent: 6077791 (2000-06-01), Detar
patent: 6143634 (2000-11-01), Wallace et al.
Kizilyalli et al., Multi-Level Metal CMOS Manufacturing with Deuterium for Improved Hot Carrier Reliability, 1998, IEE, pp 935-938.*
Kizilyalli et al., Deuterium Post-Metal Annealing of MOSFET's for Improved Hot Carrier Reliability, Mar. 1997, IEEE Electron Device Letters, vol. 18, No. 3, pp 81-83.
Kizilyalli Isik C.
Merchant Sailesh Mansinh
Roy Pradip Kumar
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Elms Richard
Lucent Technologies - Inc.
Pyonin Adam
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