Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-03-11
2001-08-07
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000
Reexamination Certificate
active
06271119
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method for a semiconductor device with a multilayer wiring structure and, more particularly, to a method for forming an interlayer dielectric film so as to get a planarization in chip size.
BACKGROUND OF THE INVENTION
The operating speed of semiconductor device decreases as the product RC (time constant) of wiring resistance (R) and parasitic capacitance (c) between wirings increases, and the parasitic capacitance (C) between wirings increases inversely proportional to the interval of wirings. Therefore, in order to enhance the operating speed of semiconductor device, it is important that the parasitic capacitance is reduced.
The parasitic capacitance between different layers can be reduced by increasing the thickness of interlayer dielectric film. On the other hand, in order to reduce the parasitic capacitance between same layers, any one of the ways to increase the wiring interval, to reduce the wiring height and to use a low-specific-permittivity interlayer insulating film is necessary of them, the ways to increase the wiring interval and to reduce the wiring height are not suitable since they go against the recent trends that, with the micro-structuring of semiconductor device, the wiring interval is decreased and the aspect ratio between wirings (wiring thickness(=wiring height)/interval of wirings) is increased. So, for wirings of same layers, it is necessary to reduce the parasitic capacitance by filling the low-specific-permittivity interlayer insulating film. Especially for part with narrow wiring interval and part with high aspect ratio between wirings, since RC (time constant) is essentially high as described earlier, it is highly necessary to fill the low-specific-permittivity interlayer insulating film.
On the other, multilayer wiring has been in wide use with the micro-structuring of semiconductor device. As the interlayer dielectric film for semiconductor device with multilayer wiring, silicon-dioxide-system insulating film is used. However, when metal such as aluminum etc. is used as the wiring material, the temperature in forming the interlayer dielectric film is limited lower than 450° C. So, PE-TEOS film is wide used as the interlayer dielectric film. PE-TEOS film is silicon dioxide film formed by plasma enhanced chemical vapor deposition using TEOS (tetraethylorthosilicate). The specific permittivity of PE-TEOS film is about 4.2 to 4.4. However, when buried insulating film is formed only by PE-TEOS film, there is room for improvement at points below. Namely, a wiring gap with wiring interval of shorter than 0.5 &mgr;m and aspect ratio of higher than 1 cannot be completely buried, and therefore a void is likely to occur between the micro-wirings. Also, the unevenness of surface is likely to increase, which may cause an etch residue of metal in dry-etching the upper metal wiring and a disconnection of upper wiring itself.
Accordingly, the method to bury a low-specific-permittivity insulating film between the micro-wirings and to planarize the surface has been needed. Such a method is known as conventional methods described below.
The first conventional method is reported by Furusawa et al. in Symposium on VLSI Technology, 1995. This method uses an interlayer dielectric film having the sandwich structure that organic SOG (spin on glass) film with a low specific permittivity of 3.0 is sandwiched by upper and lower PE-TEOS films with specific permittivity of 4.5. Here, organic SOG film is left on the entire surface without etching-back (non-etch-back process). Thus, it has the structure that organic SOG film is exposed at the sidewall of via hole.
FIGS. 1A
to
1
C are cross sectional views showing in sequence the steps of the first conventional method for making a semiconductor device. First, as shown in
FIG. 1A
, insulating film
602
is formed on the entire surface of a silicon substrate
601
, and then lower wirings
603
a
to
603
c
of metal film mainly composed of aluminum are formed using photolithography and dry etching method. On these wirings, first silicon dioxide film
604
of FE-TEOS film is thin formed as a contact layer. Further thereon, organic-contained SOG (organicSOG) film
605
with a specific permittivity of 3.0 is formed by coating-baking method. Finally, on the entire surface, second silicon dioxide film
606
of PE-TEOS film is thin formed. Thus, interlayer dielectric film
615
composed of three layers of the first silicon dioxide film
604
, organic SOG film
605
and second silicon dioxide film
606
is formed.
Then, as shown in
FIG. 1B
, by photolithography and dry etching method, via holes
608
a
,
608
b
are formed using photoresist
607
as a mask. When photoresist
607
is removed with oxygen plasma, the following method is used. For the first step, at a low pressure of 1.2 mTorr, using oxygen reactive ion etching method, the surface of organic SOG film
605
that is exposed on the sidewall of the via holes
608
a
,
608
b
is vitrified. For the second step, at a low pressure of 1 Torr, photoresist
607
is removed ashing with oxygen. Especially this step is shown in FIG.
1
B. Finally, in order to completely remove the residue of photoresist, the wet-type photoresist removal is conducted. With the above steps, the desired via holes
608
a
,
608
b
are formed in the interlayer dielectric film
615
.
Finally, as shown in
FIG. 1C
, by sputtering method, titanium film
610
and titanium nitride film
611
are formed on the entire surface. Then, by thermal CVD (chemical vapor deposition) method, tungsten film
612
is formed.
The second conventional method is disclosed in Japanese patent application laid-open No.8-107149 (1996). In this publication, the first and third embodiments are applicable to coating-system organic-contained insulating film.
FIGS. 2A
to
2
C are cross sectional views showing in sequence the steps of the second conventional method, which especially corresponds to the third embodiment in the publication. The difference between the first and third embodiments is just about whether first oxide upper layer
704
is formed over a metal conductor
703
or not. Both of the embodiments use interlayer dielectric film
710
having the sandwich structure composed of three layers of oxide liner
706
, low-permittivity film
708
and second oxide upper layer
709
. The characteristic points are that base-layer insulating film
702
is dug down when forming the metal conductor
703
, and that the oxide liner
706
is formed thinner at the side of wiring than on the top of wiring Owing to these points, a sufficient amount of low-permittivity film
708
can be buried between the wirings, thereby reducing the parasitic capacitance between the wirings. This method is explained below, referring to
FIGS. 2A
to
2
C.
First, as shown in
FIG. 2A
, insulating film
702
is formed on the entire surface of a silicon substrate
701
, and then metal film mainly composed of aluminum-copper alloy and its upper oxide layer are formed into the first oxide upper layer
704
and metal conductor
703
, using photolithography and dry etching method. In this step, insulating film
702
is dug down about 100 nm. Thereon, the oxide layer
706
of PE-TEOS film is formed. In this step, the oxide liner
706
is formed thinner at the side of wiring than on the top of wiring.
Then, as shown in
FIG. 2B
, low-permittivity film
707
of organic SOG is formed by coating-baking method.
Then, as shown in
FIG. 2C
, the low-permittivity film
707
is etched back designating time until it becomes lower than the top of the oxide liner
706
, thereby forming the low-permittivity film
708
between the metal conductors. Then, the second oxide upper layer of PE-TEOS film
709
is formed on the entire surface. As a result, the interlayer dielectric film
710
composed of three layers of oxide liner
706
, low-permittivity film
708
and second oxide upper layer
709
.
However, in the first conventional method, as shown in
FIG. 1B
, when the photoresist
607
is removed ashing with oxygen plasma
60
Dang Phuc T.
Hutchins, Wheeler & Dittmar
NEC Corporation
Nelms David
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