Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-09
2001-08-14
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S107000, C257S111000, C257S119000
Reexamination Certificate
active
06274910
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electrostatic discharge protection techniques. More particularly, the present invention relates to an electrostatic discharge protection circuit fabricated in semiconductor-on-insulator structures.
2. Description of the Related Art
Semiconductor-on-insulator (SOI) technology employs a semiconductor film overlying an insulating layer on a supporting substrate. Therefore, field effect transistors such as MOSFETs fabricated in the semiconductor film of an SOI structure have many advantages over those MOSFETs fabricated on the traditional bulk semiconductor substrates, including resistance to short-channel effect, steeper subthreshold slopes, increased current drive, higher packing density, reduced parasitic capacitance, and simpler processing steps.
However, a major obstacle to the use of SOI technology in production is electrostatic discharge (ESD) susceptibility. In bulk-substrate technology, good ESD protection levels have been demonstrated by using nMOS/CMOS buffers. However, this protection scheme is not compatible with SOI structures. For instance, thick-oxide devices are not available on an SOI substrate. Furthermore, vertical large-area low-series-resistance PN junctions are not available if the semiconductor film is thinner than 2000 Å.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an ESD protection circuit fabricated in SOI structures to functionally bypass ESD stress.
For attaining the aforementioned object, the present invention provides an ESD protection circuit fabricated on a semiconductor block on an insulating layer overlying a supporting substrate. The ESD protection circuit comprises a first N-type doped region, a first P-type doped region, a second N-type doped region and a second P-type doped region sequentially formed in the semiconductor block, and a stacked structure overlying the first P-type doped region and the second N-type doped region, wherein the first N-type doped region is more heavily doped than the second N-type doped region and the first P-type doped region is more lightly doped than the second P-type doped region.
Accordingly, the first N-type doped region, the first P-type doped region, the second N-type doped region, and the second P-type doped region constitute a semiconductor controlled rectifier as a cathode, a cathode gate, an anode gate and an anode, respectively. When ESD stresses between the first N-type doped region and the second P-type doped region, the PN junction between the first P-type doped region and the second N-type doped region enters breakdown so that the semiconductor controlled rectifier is triggered to conduct a discharge current and thus bypass the ESD stress for protecting other circuits or devices from ESD damage.
REFERENCES:
patent: 5453384 (1995-09-01), Chatterjee
patent: 5600160 (1997-02-01), Hvistendahl
Fish & Richardson P.C.
Winbond Electronics Corporation
Wojciechowicz Edward
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