Tungsten bit line structure featuring a sandwich capping layer

Details Tungsten bit line structure featuring a sandwich capping layer Tungsten bit line structure featuring a sandwich capping layer

1999-08-16

2001-05-29

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S129000

Reexamination Certificate

active

06239014

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to create a bit line structure, for a semiconductor device.
(2) Description of Prior Art
Bit line structures, for semiconductor devices such as dynamic random access memory, (DRAM), have been fabricated using conductive layers such as doped polysilicon, metal silicide, or metal. In addition these same bit line structures have been capped, or encapsulated with silicon nitride, to allow self-alignment of the bit line structure to underlying structures, or to allow self-alignment of subsequent overlying structures to the bit line structure, to be accomplished. The use of a high dielectric constant, silicon nitride layer, as a capping layer for the bit line structures, can howver result in performance degrading coupling capacitances, as a result of the proximity of adjacent conductive structures, to the silicon nitride capped, bit line structure. A solution used to lower the performance degrading coupling capacitance, has been the use of a silicon oxide layer, located between the overlying silicon nitride layer, and the underlying, conductive bit line shape. The use of the lower dielectric constant silicon oxide layer, results in a reduction in coupling capacitance when compared to counterparts fabricated only the silicon nitride capping layer.
To further increase device performance the bit line structure can be formed from tungsten, offering a sheet resistance between about 1 to 3 ohms/square, compared to counterparts fabricated from tungsten silicide layers, with a sheet resistance between about 5 to 10 ohms/square. However during the formation of the silicon oxide layer, used to reduce coupling capacitance, the surface of the underlying tungsten shape can be oxidized, resulting in unwanted consumption of tungsten, increasing the resistance of the bit line structure. This invention will teach a process sequence in which a silicon oxide layer can be used as part of a composite, or sandwich, capping layer, however avoiding the risk of oxidizing the underlying tungsten bit line. This is accomplished by initially depositing a thin underlying silicon nitride, directly on the tungsten layer, used for the bit line, followed by the deposition of the needed silicon oxide layer, and of the overlying silicon nitride layer, used for self-alignment purposes. After patterning a silicon nitride capped, tungsten bit line structure is realized, featuring the use of the silicon oxide layer, used to reduce coupling capacitance, but placed on a thin underlying silicon nitride layer, to avoid reaction with tungsten. Prior art, such as Sung et al, in U.S. Pat. No. 5,879,986, describe a silicon nitride encapsulated bit line structure, however that prior art does not feature the use of a silicon oxide layer, as a component of the capping layer, and thus allowing performance degrading coupling capacitances to occur.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a tungsten bit line structure, for a semiconductor device, with the tungsten bit line structure capped with an overlying composite insulator layer.
It is another object of this invention to use a silicon oxide layer, as a component of a composite insulator capping layer, to reduce coupling capacitance between the composite insulator capped, tungsten bit line structure, and adjacent conductive structures.
It is still another object of this invention to place the silicon oxide layer, of the composite insulator capping layer, on a thin underlying silicon nitride layer, avoiding oxidation of the surface of the tungsten bit line structure, during formation of the silicon oxide layer.
In accordance with the present invention a method of fabricating a tungsten bit line structure, capped with a composite insulator layer comprised of: an underlying, thin silicon nitride layer; a silicon oxide layer; and an overlying, capping silicon nitride layer; with the silicon oxide layer used to reduce the coupling capacitance between the bit line structure and adjacent conductive structures, is described. A bit line contact hole is formed in an insulator layer, exposing a source/drain region, located between silicon nitride encapsulated gate structures, followed by the formation of a bit line contact structure, residing in the bit line contact hole A titanium—titanium nitride layer, is deposited followed by the deposition of a tungsten layer. Deposition of a composite insulator layer, on the underlying tungsten layer, is next performed with the composite insulator layer comprised of: an underlying, thin silicon nitride layer; a silicon oxide layer, used to reduce coupling capacitance between a subsequent bit line structure, and adjacent conductive structures; and an overlying silicon nitride layer, used as the capping layer for the subsequent bit line structure. Conventional patterning procedures are next used to define a bit line shape in the composite insulator layer, followed by definition of the tungsten bit line structure, using the composite insulator shape as an etch mask. Silicon nitride spacers are then formed on the sides of the composite insulator capped, tungsten bit line structure.


REFERENCES:
patent: 5879986 (1999-03-01), Sung
patent: 5895239 (1999-04-01), Jeng et al.
patent: 6025645 (2000-02-01), Tomita

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