Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-16
2001-01-09
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S372000, C257S379000, C257S533000, C257S536000
Reexamination Certificate
active
06172405
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. HEI 10(1998)-203387 filed on Jul. 17, 1998, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a production process therefor. More particularly, the invention relates to a semiconductor device such as a dynamic threshold voltage transistor in which a gate electrode is connected to a well region and a production process therefor.
2. Description of Related Art
For reducing power consumed by a CMOS circuit using a MOSFET, decreasing supply voltage is one of the most effective means. However, if the supply voltage is simply decreased, a driving current for the MOSFET declines and the operating speed of the circuit slows. It is known that this phenomenon becomes notable where the supply voltage becomes lower than the triple of the threshold voltage of a transistor.
In order to prevent this phenomenon, the threshold voltage may be lowered. However, a decline in the threshold voltage may give rise to a problem that leakage current when the MOSFET is off (also referred to as off-leak hereinafter) increases. For this reason, the lower limit of the threshold voltage is restricted within such a range that this problem does not occur. Such restriction to the lower limit of the threshold voltage also sets limits to reduction of power consumption since it corresponds to the lower limit of the supply voltage.
In order to provide relief from this problem, conventionally proposed is a dynamic threshold voltage MOSFET (DTMOS) using an SOI substrate which allows a high driving current to be produced from a low supply voltage by reduction of an effective threshold when the MOSFET is on (A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation by F. Assaderaghi et al., IEDM94 Ext. Abst. P.809(1994)). Also proposed are dynamic threshold voltage transistors without using the expensive SOI substrate but using bulk substrates (Japanese Unexamined Patent Publication No. HEI 10(1998)-22462 and Novel Bulk Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation (SITOS) and Gate to Shallow Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS by H. Kotaki et al., IEDM Tech. Dig., p.459, 1996). Both the MOSFETS can reduce the effective threshold voltage when they are on, because gate electrodes and substrates (or well regions) are electrically short-circuited.
FIGS.
27
(
a
) and
27
(
b
) show N-type dynamic threshold voltage transistors using the former SOI substrate. FIG.
27
(
a
) shows a transistor of a complete depletion type and FIG.
27
(
b
) shows a transistor of a partial depletion type. In the figures, reference numeral
111
denotes a substrate,
112
denotes a buried oxide film layer,
113
denotes a body,
114
denotes a source region,
115
denotes a drain region,
116
denotes a gate insulating film, and
117
denotes a gate electrode. The gate electrode
117
is electrically connected to the p-type body
113
via a contact hole, though not shown. Here, the complete depletion means that the body is completely depleted beneath the gate electrode and the partial depletion means that the body is partially undepleted beneath the gate electrode. It is noted that P-type transistors can be formed by reversing polarity (a type of conductivity) shown in the figures.
FIG. 28
shows an N-type dynamic threshold voltage transistor using the latter bulk substrate. It is noted that a P-type transistor can be formed by reversing the polarity (a type of conductivity) shown in the figure. In the figure, reference numeral
211
denotes a substrate,
212
denotes an N-type well region (a deep well region),
213
denotes a P-type well region (a shallow well region),
214
denotes a buried high-concentration region,
215
denotes a trench isolation region,
216
denotes a source region,
217
denotes a drain region,
218
is a gate insulating film and
219
denotes a gate electrode. The gate electrode
219
is electrically connected to the shallow well region
213
via a contact hole though this connection is not shown. A transistor formed in a single shallow well region is simply referred to as a device hereinafter.
Now explanation is given to the principle of operation of the dynamic threshold voltage transistor using the bulk substrate. It is noted that the transistor using the SOI substrate also operates on substantially the same principle. In the above-mentioned transistor, when the potential of the gate electrode is at a low level (when the transistor is off), the potential of the shallow well region is also at a low level. Accordingly, the effective threshold voltage does not differ from that of a common MOSFET, and the value of leakage current is the same as that of the common MOSFET.
When the potential of the gate electrode is at a high level (when the transistor is on), the potential of the shallow well region is also at a high level. The effective threshold voltage decreases due to a substrate bias effect and the driving current increases as compared with the common MOSFET. Therefore, a large driving current can be obtained at a low supply voltage while a low leakage current is maintained.
Next, explanation is given to device isolation with the dynamic threshold voltage transistor using the bulk substrate. The potential in the shallow well region varies depending on the potential of the gate electrode. For this reason, a trench isolation region is formed between devices for isolating them to prevent interference therebetween. The depth of the trench isolation region is set such that the shallow well regions of adjacent devices are electrically separated. That is, the depth of the trench isolation region is so set that a depletion layer extending from a junction of the shallow well region and the deep well region does not contact to a depletion layer extending from a junction of the shallow well region with the deep well region of the adjacent device.
For making the most of the substrate bias effect and realizing a high-speed operation, a change in the potential of the gate electrode must be transmitted to the shallow well region quickly. For this purpose, the buried high-concentration region is constructed to be sandwiched by regions having low impurity concentrations, in FIG.
28
. This construction enables electrical resistance in the shallow well region to decrease and a change in the potential of the gate electrode to be transmitted to the shallow well region immediately. At the same time, since the impurity concentration in a channel region can be reduced, a low threshold can be realized and a junction capacitance between the source region and the shallow well region and a junction capacitance between the drain region and the shallow well region can be kept small.
As described above, in operation of the dynamic threshold voltage transistor, a change in the potential of the gate electrode is required to be transmitted to the shallow well region quickly. Time necessary for this transmission is explained with use of FIGS.
29
(
a
) and
29
(
b
). FIG.
29
(
a
) is a schematic diagram of a dynamic threshold voltage transistor using a bulk substrate and FIG.
29
(
b
) is an equivalent circuit diagram thereof. In the figures, reference numeral
311
denotes a deep well region,
312
denotes a shallow well region,
313
denotes a source region,
314
denotes a drain region,
315
denotes a gate insulating film,
316
denotes a gate electrode,
317
denotes a gate input terminal,
318
denotes a depletion layer region extending from a junction of the source region and the shallow well region,
319
denotes a depletion layer region extending from a junction of the drain region with the shallow well region,
320
denotes a gate depletion layer region,
321
denotes a depletion layer region extending from a junction of the shallow well region and the deep well region,
322
denotes a source input terminal,
Iwata Hiroshi
Shibata Akihide
Sharp Kabushiki Kaisha
Wojciechowicz Edward
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