Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-08-19
2001-01-30
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06182265
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for encoding a channel using a parallel convolutional encoder, and in particular, to an improved method for encoding a channel using a parallel convolutional encoder which is capable of enhancing the performance of a digital wireless communication using a convolutional encoding and interleaving operation.
2. Description of the Conventional Art
FIG. 1
illustrates a conventional channel encoder in which one frame data inputted through a frame input data register
1
in accordance with a control of a micro controller is sequentially inputted an encoder RAM (ERAM)
4
in accordance with a control of a write address controller
2
.
The data stored in the ERAM
4
is sequentially read earlier than the time when the data is computed at a boundary of the next frame and are inputted into a convolutional encoder
6
through a parallel-serial converter
5
for thereby generating a code symbol, and the code symbol generated for performing an interleaving operation is stored into an interleaver RAM (IRAM)
7
in accordance with a control of a write address controller
8
for thereby reading the data in a form of row at a normalized time in accordance with a control of a read address controller
9
at a boundary of the frame for thereby completing a channel encoding operation.
FIG. 2
illustrates a timing of a conventional channel encoder. As shown therein, in Step S
1
, the micro controller writes input data into a frame input data register
1
in accordance with a data request interrupt signal.
In Step S
2
, the input data stored in the frame input data register
1
is sequentially stored into the ERAM
4
.
When the data of one frame is all inputted, the convolutional encoding operation becomes a ready state and waits an ERAM reading timing.
The input data of one frame is buffered into the ERAM
4
and then are read for thereby implementing a convolutional encoding operation. The above-described operation is simply performed but there is a problem in that the data should be written into the IRAM
7
within one frame's time, and one frame should be equally divided to thereby read the data stored in the IRAM
7
at a normalized time.
In order to control the above-described timing, the data should be written into the IRAM
7
between the final IRAM read time of the previous frame and the initial IRAM read time of the current frame, and only the data used at the time when the data is read from the IRAM
7
in a form of row at the above-described time are written into the IRAM, so that the IRAM write and read operations are performed at the same time.
There is a limit in that the micro controller stores frame input data into the frame input data register
1
by avoiding the time when the data are read from the ERAM
4
and then encoded. In addition, additional control operation is required for adjusting the position of a data request interrupt.
In Steps S
3
and S
4
, the data stored in the ERAM
4
is sequentially read at the boundary of the frame for a predetermined time, and the convolutional encoding operation is performed with respect to the first frame.
In Step S
5
, the code symbol from the convolutional encoder is sequentially stored into the IRAM
7
from the first address.
As shown in
FIG. 2
, the operations for writing and reading the data into/from the IRAM are performed. Therefore, the data read at the initial time in a form of row is stored and written into the IRAM
7
.
The data read from the IRAM
7
at the time which is obtained by equally dividing one frame at the boundary of the frame in Step S
6
for thereby implementing a channel encoding operation of the initial frame, and then the input data of the second frame is received in Step S
7
, and the channel encoding operation of the second frame is performed in the same manner as the first frame.
Namely, in order to implement the channel encoder which used a convolutional encoding operation and an interleaving operation, the ERAM
4
and the control circuit are required for buffering the frame input data. In addition, complicated timing control circuits are required for generating an address for performing a write and read operation within one frame time.
In addition, it is impossible to write the frame input data into the frame input data register
1
while the convolutional encoding operation is performed and the data stored in the ERAM
4
is read by the micro controller. In addition, in order to overcome the above problem, the position of the data request interrupt should be adjusted for thereby additionally requiring a control operation.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for encoding a channel using a parallel convolutional encoder which overcomes the aforementioned problems encountered in the conventional art.
It is another object of the present invention to provide a method for encoding a channel using a parallel convolutional encoder which is capable of inputting data into a frame input data register and, at the same time, encoding the data using a parallel convolutional encoder and processing an interleaving operation using two interleaver RAMs without using a frame input data buffer RAM for decreasing the number of RAM control logic hardware of a channel encoder and implementing a simple protocol when changing a micro controller and a frame input data packet by overcoming the problems encountered in the conventional art which uses a RAM storing a frame data and another RAM interleaving a code symbol which is an output from the convolutional encoder when implementing a channel encoder using a convolutional encoding and interleaving operation.
In order to achieve the above objects, there is provided a method for encoding a channel using a parallel convolutional encoder according to a first embodiment of the present invention which includes the steps of performing an encoding operation using a parallel convolutional encoder at the time when data is inputted into a frame input data register for implementing a channel encoding operation and generating a code symbol, and storing the generated code symbol into an interleaver RAM which is alternately selected by the frame unit.
In order to achieve the above objects, there is provided a method for encoding a channel using a parallel convolutional encoder according to a second embodiment of the present invention which includes the steps of inputting frame input data into a frame input data register in accordance with a control of a micro controller for a channel encoding operation without using an input data buffer RAM, generating a code symbol by performing an encoding operation of the frame input data using a parallel convolutional encoder, sequentially storing the code symbol into an interleaver RAM which is alternately selected by the frame unit, and reading the data stored in the interleaver RAM and performing an interleaving operation based on the interleaver algorithm for the next frame.
Additional advantages, objects and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
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Byun Kyung Jin
Han Ki Cheon
Kim Kyung Soo
Lim In Gi
Yeon Kwang Il
Antonelli Terry Stout & Kraus LLP
Cady Albert De
Chase Shelly A
Electronics and Telecommunication Research Institute
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