Sram cell structure

Details Sram cell structure Sram cell structure

1997-09-15

1998-10-20

Le, Vu A.

Static information storage and retrieval

Systems using particular element

Flip-flop

365149, 365174, G11C 700

Patent

active

058256849

ABSTRACT:
An SRAM transistor cell on a doped semiconductor substrate comprises two access FET transistors and two storage FET transistors. A first load capacitor has a plate connected to a first node with the other plate connected to the power supply. A second load capacitor has a plate connected to the second node with the other plate connected to the power supply, a bit line and a bit line bar. The first storage transistor drain connects to the first node. The second storage transistor drain connects to the second node. The storage transistors have interconnected sources. The first node connects via a first interconnection line to the second transistor gate. The second node connects via a second interconnection line to the first transistor gate. First and second access transistor gates connect to a wordline. The first access transistor drain connects to the first node. The second access transistor drain connects to the second node. The first access transistor source connects to the bit line. The second access transistor source connects to the bit line bar.

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patent: 5051951 (1991-09-01), Maly et al.
patent: 5198706 (1993-03-01), Papaliolios
patent: 5330927 (1994-07-01), Lee
patent: 5376814 (1994-12-01), Lee
patent: 5377139 (1994-12-01), Lage et al.

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