Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
1999-12-10
2001-09-11
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
Reexamination Certificate
active
06288961
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device for reading charges stored in a capacitor in a memory cell and a data reading method thereof and, more particularly, to a dynamic random access memory (DRAM) or a ferroelectric memory.
FIG. 1
shows a circuit arrangement of a basic ferroelectric memory as an example of a semiconductor memory device for reading charges stored in a capacitor in a memory cell. This circuit comprises memory cells MC, dummy cells DMC, a sense and rewrite amplifier (sense amplifier)
18
, a word line i
19
, a word line (i+1)
20
, a dummy word line a
21
, a dummy word line b
22
, a plate line i
23
, a plate line (i+1)
24
, a dummy plate line a
25
, a dummy plate line b
26
, a pair of bit lines BL and {overscore (BL)} as a differential pair, transistors
300
and
301
for selecting a column, a column selection line
302
, and a pair of common read data lines DL and {overscore (DL)}. The memory cells MC have ferroelectric capacitors
10
and
11
and selection transistors
14
and
15
, respectively. The dummy cells DMC also have ferroelectric capacitors
12
and
13
and selection transistors
16
and
17
, respectively.
In the above arrangement, as the direction of the electric field in the ferroelectric memory and the direction of polarization (these two directions match), the direction from the plate line to the bit line is defined as a positive direction. In the ferroelectric memory, the bit lines have a level difference in accordance with direction of polarization of a ferroelectric capacitor storing data. The read operation will be described in detail with reference to the timing chart of FIG.
2
. The bit line is precharged to 0 (V) in advance. A word line connected to a cell to be selected is selected, and in this state, a plate line is selected. After the potentials of the pair of bit lines BL and {overscore (BL)} change, the sense and rewrite amplifier
18
is activated to set one of the bit lines BL and {overscore (BL)} at high level and the other at low level. In the circuit shown in
FIG. 1
, when the ith word line
19
is selected, the dummy word line
21
is selected. When the (i+1)th word line
20
is selected, the dummy word line
22
is selected.
Assume that the power supply voltage is 3 (V), and the potentials of the selected plate line and dummy plate line become 3 (V) at maximum. Also, assume that the maximum value of the potentials of the selected word line and dummy word line is boosted to a voltage (e.g., 4.5 (V)) for compensating for a drop in threshold voltage by a cell selection transistor and dummy cell selection transistor such that the high potential of the pair of bit lines BL and {overscore (BL)} is transmitted to the capacitor.
When polarization in the capacitor in the selected memory cell is directed upward (from the plate line side to the bit line side), polarization inversion does not occur because the direction of polarization matches that of the electric field. In this case, since the amount of charges removed from the cell is small, the level of the bit line is low. To the contrary, when polarization is directed downward (from the bit line side to the plate line side), polarization inversion occurs because polarization and the electric field are directed in opposite directions. In this case, since the amount of charges removed from the cell is large, the level of the bit line is high. Hence, when the areas of the ferroelectric capacitors
12
and
13
in the dummy cells are set to generate the intermediate level between the bit line level when polarization inversion occurs and that when polarization inversion does not take place, the level difference between the bit lines BL and {overscore (BL)} can be sensed by the sense and rewrite amplifier
18
.
The scheme of sensing the bit line level while setting the plate line at high level, as shown in
FIG. 2
, is called “during plate pulse sensing” for the descriptive convenience. Such a data read operation is disclosed in U.S. Pat. No. 4,873,664. This patent describes that the areas of the ferroelectric capacitors
12
and
13
in the dummy cells are set to be twice those of the ferroelectric capacitors
10
and
11
in the memory cells to generate the intermediate potential. The dummy capacitor in the dummy cell must be biased such that the dummy cell does not operate in the polarization inversion region, i.e., polarization is always directed upward (from the plate line to the bit line).
To clarify the problem of the conventional circuit, the bit line level to be sensed will be described using a graphic solution of the hysteresis characteristics of the ferroelectric capacitor. The positive direction is defined as a direction from the plate line to the bit line. Let V
f
be the voltage applied to the ferroelectric capacitor. Referring to
FIG. 3
, while the potential relationship is changing from (a) to (b), the amount QB of charges in the bit line is kept unchanged because the bit line is not charged/discharged. This situation can be represented as:
Q
B
=+C
B
×0−P(0)A=+C
B
(3−V
f
)−P(V
f
)A (1)
where A is the area of the ferroelectric capacitor, and C
B
is the parasitic capacitance of the bit line.
Equation (1) can be rewritten as:
P(V
f
)=P(0)+C
B
(3−V
f
)/A (2)
Based on equation (2), the voltage V
f
applied to the ferroelectric capacitor in during plate pulse sensing is given by the coordinate value on the abscissa at the intersection between the hysteresis characteristics P=P(V
f
) of the ferroelectric capacitor and P=P(0)+C
B
(3−V
f
)/A. Therefore, the voltage V
f
when polarization inversion occurs from polarization directed downward (high level), the voltage V
f
when polarization inversion does not occur from polarization directed upward (low level side), and the voltage V
f
by the dummy cell are obtained as shown in FIG.
4
. Each bit line potential is also obtained on the basis of equation (3) as shown in FIG.
4
.
V
B
=3−V
f
(3)
According to the hysteresis characteristics of the cell, the gradient of P(V
f
)A with respect to the voltage V
f
is proportional to the electrostatic capacitance of the cell. Pieces of information stored in the bit lines BL and {overscore (BL)} belonging to the selected column
302
are sent to the common read data lines DL and {overscore (DL)} through the transistors
300
and
301
for selecting the column, respectively.
Generally, a sense amplifier is constituted by a flip-flop including p-channel MOS (PMOS) transistors
217
to
219
and n-channel MOS (NMOS) transistors
220
to
223
, as shown in FIG.
5
. The PMOS transistor
217
and NMOS transistor
223
serve as a power switch of the flip-flop. When a gate
206
of the Transistor
217
is at level “0”, and a node
203
of the transistor
223
is at level “1”, the flip-flop is activated to start the sense operation. Normally, to decrease the through current flowing from a power supply T to a ground point
2
through the PMOS and NMOS transistors in the flip-flop, the ON timings of the transistors
217
and
223
as a power supply switch are shifted. When common read data lines are to be precharged to the power supply voltage, the switching speed of the data line DL or {overscore (DL)} is determined on the basis of the change speed from high level to low level. Therefore, the sense amplifier drives the bit line from the NMOS transistor side.
As is apparent from
FIG. 4
, the electrostatic capacitance of the dummy cell is about twice that of the cell capacitor in the cell on the low level side. For example, assume that before the start of the sense operation, the potential of the bit line BL on the low level side is 1.0V, and the potential of the bit line {overscore (BL)} on the dummy cell side is 1.1V. Since the potential of the gate (bit line BL) of the NMOS transistor
221
for reducing the potential of the bit line {overscore (BL)} in the sense amplifier is slightly lo
Ogiwara Ryu
Tanaka Sumio
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Le Vu A.
LandOfFree
Semiconductor memory device for reading charges stored in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device for reading charges stored in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device for reading charges stored in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2525615