High-performance interconnect

Details High-performance interconnect High-performance interconnect

1999-01-20

2001-05-29

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S041000, C326S047000, C326S101000, C257S499000, C257S503000, C333S012000

Reexamination Certificate

active

06239615

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the field of integrated circuits. More specifically, the present invention provides techniques and circuitry for reducing parasitics, crosstalk, noise, and other similar properties when propagating signals on the interconnect lines of an integrated circuit, which will improve the performance and reliability of the integrated circuit.
In an electronic circuit, such as a integrated circuit or printed circuit board, there are many interconnections between the various circuits and devices. These interconnections or interconnect lines may be made using wires, conductive interconnect layers, metal lines, polysilicon lines, polysilicide lines, and diffusion layers, just to name a few. To allow for efficient layout of the integrated circuits, interconnect lines are typically grouped together and run adjacent to another, or organized in a bus structure.
Various types of integrated circuits, all of which use interconnect lines, include microprocessors, static random access memories (SRAMs), erasable-programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), Flash EEPROM memories, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), among others.
In particular, PLDs are well known to those in the electronic art. Such programmable logic devices are commonly referred as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs, PLDs, EPLDs (Erasable Programmablc Logic Devices), EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for a specific application. Such devices include, for example, the well-known, Classic™, and MAX® 5000, MAX® 7000, and FLEX® 8000, FLEX® 10K programmable integrated circuits made by Altera Corp.
PLDs are generally known in which many logic array blocks (LABs) are provided in a two-dimensional array. LABs contain a number of individual programmable logic elements (LEs) which provide relatively elementary logic functions such as NAND, NOR, and exclusive OR. Further, PLDs have an array of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the LABs and LEs. As can be appreciated, many interconnect lines are used to facilitate the interconnections between the various logical features. Interconnect are conductors on the integrated circuit which are used to wire and connect together the devices, gates, transistors, logical blocks, pads, and other components. As integrated circuits become larger and denser, there will be greater numbers of interconnect lines per integrated circuit. It becomes increasingly important to improve the techniques and architectures used for interconnecting the elements and routing signals between the logic blocks. The performance of the integrated circuit depends in part on the performance of the signals through the interconnect lines.
An example of one factor that reduces the performance (and may also affect the functional reliability of the logical circuitry) of the interconnect is crosstalk or cross-coupling between the interconnect lines. In particular, crosstalk interference glitches which may occur on rising and falling edges of the main signal are amplified by the receiving buffer if these glitches are in the high gain region of that buffer. This effect may lead to double clocking, which would create logical errors in the function circuitry. Further, the perfonnance of the interconnect lines may also be slower because of the increased propagation delay due to the crosstalk.
These problems and concerns will become more significant as it becomes possible to fabricate denser integrated circuits. With increased microminiaturization, interconnect wires on the integrated circuit will be closer together. According to well-known physics principles, a shorter distance between the interconnect leads to an increase the capacitance between the interconnect lines. An increased capacitance between the interconnect lines increases the crosstalk or cross-coupling between the interconnect lines.
As can be seen, improved techniques and circuitry for interconnecting signal lines are needed, especially techniques for improving interconnect lines and their use to provide improved performance and greater integrity and reliability.
SUMMARY OF THE INVENTION
The present invention provides various techniques for improving the performance of interconnect lines and conductors on an integrated circuit. These techniques include arranging, laying out, and fabricating the signal conductors so the parasitic coupling capacitances are minimized and parasitic resistance is reduced.
The interconnect may be implemented using multiple layers or levels of conductive material. Signal conductors may be interleaved with shielding conductors to reduce cross-coupling between signal lines. Signal conductors are arranged and positioned to minimize the length at which two signal conductors are run in parallel to another, and in relatively close proximity. For example, signal conductors in a first layer are not positioned on top of or beneath other signal conductors in a different layer. Conductors are widened as possible to reduce resistance.
The conductive material to implement the interconnect may include aluminum and copper conductors. Low k dielectrics may be used between the conductors to minimize parasitic capacitances.
Further techniques to provide high-performance interconnect include line segmentation where a signal line is divided into multiple line segments. Between the line segments, there are unidirectional or bidirectional buffers to provide greater signal drive capability.
Glitch filtering buffers may be used at the input to the logic circuits such as LABs and LEs. Cross-coupling between the signal lines may produce glitches. Glitches may cause effects such as double clocking which would lead to functional errors. The glitch filtering buffers would minimize the effects of these glitches, and ensure the logical functionality is not disturbed improperly.
In an embodiment, the invention is an integrated circuit including a first level of interconnect conductors having a first signal conductor; and a second level of interconnect conductors having a second signal conductor and a shielding conductor, where the second signal conductor is formed adjacent to the shielding conductor, and the shielding conductor is formed above the first signal conductor. Furthermore, there may be a third signal conductor in the second level that is formed adjacent to the shielding conductor. This third signal conductor would not be directly above the first signal conductor.
In another embodiment, the invention is an integrated circuit including a first and second level of interconnect conductors, where the second level is formed above the first level. The interconnect conductors in the first level are formed on top of interconnect conductors in the second level, where shielding conductors in the second level are on top of signal conductors in the first level, and signal conductors in the second level are on top of shielding conductors in the first level.
In a further embodiment, the invention is an integrated circuit including interconnect lines; logical circuits to receive signals via the interconnect lines; and a buffer, connected between one of the interconnect lines and one of logical circuits. The buffer filters glitches in signals received from the interconnect lines. The glitch filter may include a first transistor and second transistor connected between a first and second voltage supply, and a third transistor having a control electrode connected to a node between the first and second transistors. The third transistor is connected between one of the voltage supplies and control electrodes of the first and second transistors.
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