Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-04-30
2001-07-10
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S308000, C257S309000
Reexamination Certificate
active
06259127
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to containers having roughened or rugged surfaces, and more particularly to capacitor containers for integrated circuits.
Recent advances in the miniaturization of integrated circuits have led to smaller chip areas available for devices. High density dynamic random access memory chips (DRAMs), for example, leave little room for the storage node of a memory cell. Yet, the storage node (capacitor) must be able to store a certain minimum charge, determined by design and operational parameters, to ensure reliable operation of the memory cell. It is thus increasingly important that capacitors achieve a high stored charge per unit area.
Traditionally, capacitors integrated into memory cells have been patterned after the parallel plate capacitor. An interlayer dielectric material is deposited between the deposition of two conductive layers, which form the capacitor plates. Several techniques have recently been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area occupied by the cell. These include the use of new high dielectric materials between the plates. Other techniques concentrate on increasing the effective surface area of the plates by creating folding structures, such as trench or stacked capacitors. Such structures better utilize the available chip area by creating three dimensional shapes to which the conductive plates and interlayer dielectric conform.
FIG. 1
, for example, illustrates a container capacitor structure
10
for a DRAM memory cell. An insulating or dielectric layer
12
, such as boron phosphosilicate glass (BPSG), is planarized and patterned with a photolithographic mask. The dielectric layer
12
is then etched through the resist mask
24
between a pair of gate electrodes
14
to an underlying silicon substrate, thus forming the container structure
10
. The etch may select against nitride insulation of the gate electrodes
14
, for example, including nitride sidewall spacers
22
. The container
10
is essentially A a cylindrical cavity, but it is illustrated in
FIG. 1
in schematic cross-section, for simplicity, without showing the backwall of the cylinder. A conductive layer (not shown in
FIG. 1
) would then be conformally deposited over the walls of the container
10
to serve as the bottom plate. The interlayer dielectric and top plate would be successively deposited over the bottom plate, forming a capacitor.
The surface area of the capacitor plates, and thus the capacitance of the memory cell, may also be increased by providing a roughened or texturized plate surface. Roughened or rugged polycrystalline silicon (polysilicon, or simply poly) in the form of hemispherical silicon grains (HSG), for example, has been utilized for the bottom plate of the capacitor. The resultant increase in effective area of the plates, has been observed to increase the capacitance of a storage node by more than 60%.
At the same time, the formation of HSG also increases the thickness of the bottom plate, generally by more than 500 Å and often closer to 600 Å. For the container structure
10
of
FIG. 1
, this added thickness over the container walls still leaves adequate space within the container
10
for additional layers in an upper portion
19
. The added thickness may become critical, however, at a bottom portion
20
of the container
10
, which is narrowly confined between the gate electrodes
14
. In high-density DRAM chips, the pair of gate electrodes
14
are less than 0.35 microns (3,500 Å) apart. Sidewall spacers
22
, which isolate the gate electrodes
14
from the capacitor to be formed, occupy 700 Å on either side of the container
10
cross-section, leaving a diameter of only about 2,100 Å for the remainder of the capacitor structure within the bottom portion of the container
10
. These 2,100 Å may easily be filled by the bottom plate to be formed of an amorphous or polysilicon layer (about 500 Å around the container circumference) and the HSG formed over the silicon layer (about 600 Å). These thicknesses represent reductions in the radius of the container and must be doubled in calculating the reduction of the container diameter.
It can be seen, then, that the formation of HSG for the bottom plate is likely to short across the entire bottom portion
20
of the container
10
. Such shorting and consequent loss of capacitance is even more likely, if not assured, as integrated circuit dimensions are further scaled down. In fact, prior art storage node capacitors of similar configuration have filled the bottom portion
20
with a conductive plug, purposefully shorting the bottom portion
20
and forming HSG over the walls of the upper portion only. Thus, the surface area of the bottom portion
20
does not contribute to the surface area of the bottom plate and significant losses in capacitance result.
SUMMARY OF THE INVENTION
Disclosed is a container in an integrated circuit, including a capacitor bottom plate having a partially rugged surface, and a method for making the same.
The method involves the formation, in an insulating dielectric layer, of a container structure having an upper portion and a bottom portion. A first conductive layer is conformally deposited over the container's interior surfaces. The bottom portion is isolated with a protective film. Thereafter, a conductive rugged layer is formed on the interior surface of the container's upper portion. The protective film isolating the bottom portion may then be removed.
In a first preferred embodiment, the protective film comprises a thick layer of insulating material, such as BPSG, which is deposited to substantially fill the container. An optional anneal aids reflow of BPSG to ensure filling of the bottom portion. The protective film should be recessed down to about the top of the bottom portion, leaving the upper portion substantially free of the protective film. The rugged layer is then formed, in the form of hemispherical silicon grains, on the surface of the upper portion. The protective layer should then be stripped away.
In a second preferred embodiment, the protective film comprises a thin, conformal insulating layer over the conductive layer, and a filler. The insulating layer is preferably an oxide and the filler is preferably photoresist. As in the first preferred embodiment, the protective layer is recessed to about the top of the bottom portion, though this recessing step may require two sub-steps: a first step for recessing the filler and a second step for recessing the thin insulating layer. Thereafter the process is essentially the same as that described above with reference to the first preferred embodiment.
Thus, the present invention discloses a capacitor structure wherein a capacitor bottom plate conforms to a container which has a bottom portion and an upper portion. The bottom plate comprises a relatively smooth conductive layer within the bottom portion of the container and a rugged conductive layer within the upper portion of the container. The interlayer dielectric and top conductive plate may then be deposited over the bottom plate, as provided for in the prior art.
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Cao Phat X.
Chaudhuri Olik
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
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