Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1997-07-10
2001-07-24
Nguyen, Than (Department: 2759)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S003000, C711S101000, C711S118000, C711S206000, C345S205000, C345S504000, C707S793000, C708S203000, C704S500000
Reexamination Certificate
active
06266753
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to the field of multi-media integrated-circuit controllers for use with computer systems. In particular, the present invention is directed toward a virtual memory manager for use with multi-media controllers.
BACKGROUND OF THE INVENTION
Prior art computer systems generally employed a graphics controller (e.g., VGA, SGVA, or the like) such as illustrated in FIG.
1
.
FIG. 1
is a block diagram illustrating major components of a computer system
100
provided with display controller
120
(e.g., Video Graphics Adapter (VGA), Super VGA (SVGA) or the like). Display controller
120
may generate pixel data for display
180
(e.g., CRT, flat panel display or the like) at a rate characteristic of the refresh rate of display
180
(e.g., 60 Hz, 72 Hz, 75 Hz, or the like) and horizontal and vertical resolution of a display image (e.g., 640×480 pixels, 1024×768 pixels, 800×600 pixels or the like). A continuous stream of pixel data may be generated by display controller
120
at the characteristic rate of display
180
.
Display controller
120
may be provided with a display memory
130
which may store an entire frame of pixel data in text, graphics, or video modes for output to display
180
. Host CPU
110
may be coupled to display controller
120
through bus
150
and may update the contents of display memory
130
when a display image for display
180
is to be altered. Bus
150
may comprise, for example, a PCI bus or the like. System memory
160
may be provided coupled to Host CPU
110
for storing data.
Hardware MPEG decoder
140
may be provided to decode MPEG video data from an MPEG video data source (e.g., CD-ROM or the like) and output decoded video data to system memory
160
or directly to display memory
130
. However, with the advent of increasingly powerful and faster microprocessors (e.g., Pentium™ or PowerPC™ processor or the like) it may be possible to implement MPEG decoding (or the like) entirely within software operating within host CPU
110
.
In recent years, “multi-media” devices for computers have become popular. Multi-media, as the name implies, encompasses a number of different types of functions, such as 2-D and 3-D graphics, animation, Full Motion Video™, audio, and the like. Such devices may be used for games or for business use (e.g., teleconferencing).
Unfortunately, implementation of multi-media technology has been hampered by the lack of any coherent standard for various discreet multi-media devices (graphics controllers, CD-ROM or DVD controllers, sound cards, modems, and the like). As a result, a user may become frustrated to discover that different devices conflict with one another or will not work within his or her system.
Some attempts have been made to provide better compatabilty between multimedia devices. For example, Microsoft® has promoted the use of Plug and Play™ technology. Plug and Play™ is a standard by which various peripheral devices may be inserted into a computer system which will automatically configure the system and resolve any device conflicts.
However, even with such systems, other drawbacks are present. For example, to provide realistic three dimensional (3-D) imaging, considerable processor power may be required. Users may be reluctant to discard existing personal computer (PCs) in order to take advantage of new 3-D software.
FIG. 2
is a block diagram of one apparatus which attempts to solve this problem. The apparatus of
FIG. 2
is described in more detail in
Talisman: Commodity Realtime
3
D Graphics for the PC
by Jay Torborg and James T. Kajiya (Microsoft Corporation, Aug. 21, 1996) incorporated herein by reference. In
FIG. 2
, a single multi-media device may be provided as a plug-in card for a PC. The multi-media device may be provided with a media signal processor (MSP)
210
coupled to a system bus
200
such as a Peripheral Communications Interface (PCI) or the like.
Media I/O device
230
, providing an interface for joysticks or the like (e.g., USB
1344
or the like) may be provided coupled to MSP
210
, along with Audio CODEC (audio modem)
240
. Polygon Object Processor
250
may render
3
-D images of polygons. Image layer compositor
260
may combine a number of image layers or elements using a compositing buffer to generate an output image.
Graphics memory
270
may comprise a RDRAM or other high-speed memory. Video output may pass through COMP/DAC
280
(e.g., decompressor, RAMDAC, and the like) for color conversion and output to a display.
One disadvantage of the design of
FIG. 2
is that each of the various chips may have intensive processing requirements. Graphics rendering chips
250
and
260
may have as many gates as a Pentium™ and Pentium™ PRO™ processor, respectively. Thus, the device of
FIG. 2
may be relatively complex and expensive. Moreover, the many of the functions served by the apparatus of
FIG. 2
may be able to be performed using more advanced host microprocessors, such as the Intel® MMX™ processor or its progeny and successors.
FIG. 3
is a block diagram of another approach to an improved multi-media controller. In the apparatus of
FIG. 3
, an advanced microprocessor communicates with a multimedia controller
310
over an Accelerated Graphics Port (AGP)
300
which may be a PCI-like type communications bus provided with specialized and enhanced communications features. Multimedia controller
340
incorporates may of the functions of the elements of the apparatus of FIG.
2
and in addition may rely upon an enhanced host processor to perform some multi-media functions. Multi-media controller
310
may be coupled to RDRAM
320
which may be used to store image data.
The apparatus of
FIG. 3
has the advantage of being able to interface with newer processor designs. However, the apparatus of
FIG. 2
may be more suitable as an upgrade to existing computers. In either design, however, the size of the semiconductor devices may become unwieldy and cost prohibitive due to the complexity of the designs and the functions to be performed. Thus, it remains a requirement in the art to provide a multi-media controller which preforms required multi-media functions with a minimal number of gates.
One proposal for simplifying graphics controller architecture is to unify or partially unify display memory with main memory of a computer. Referring back to
FIG. 1
, note that display memory
130
comprises an additional memory to system memory
160
. Some have argued that such a system is duplicative, and that unifying the two memories
130
and
160
would reduce overall memory requirements and allow for greater component integration.
Such a system may reduce the amount of memory required for a computer system, and thus reduce overall cost of the computer. Intel® Corporation has proposed a version of Unified Memory Architecture (UMA) in which display memory is formed from a part of system memory. While such a system may reduce component count, it may also create bandwidth bottlenecks.
In particular, a CRT or other type of display requires a constant stream of data in order to generate a display image. At higher resolutions and refresh rates, this data rate may be fairly high. If the display needs to access main memory for a significant period of time, such accesses may hamper overall CPU performance. To overcome the deficiencies of UMA, the assignee of the present application has proposed a solution known as Partially Unified Memory Architecture or PUMA.
Reference is made Bril et al., co-pending U.S. patent application Ser. No. 08/624,128 (0455-VDSK) entitled “PARTIALLY UNIFIED MEMORY ARCHITECTURE”, now abandoned and incorporated herein by reference. A memory controller in a Partially Unified Memory Architecture controls allocation of memory requests between one or more memory areas to enhance the performance of a display controller. The memory controller receives memory cycle requests from at least one subsystem including a display controller. A cycle distributor allocates requests to Main Memory Display Memory and Dedicated D
Hicok Gary D.
Michelsen Jeffery M.
Bell Robert P.
Cirrus Logic Inc.
Nguyen Than
Rutkowski Peter
Shifrin Dan
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