Semiconductor device including tester circuit suppressible...

Details Semiconductor device including tester circuit suppressible... Semiconductor device including tester circuit suppressible...

1999-12-13

2001-06-05

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000, C714S719000, C714S733000

Reexamination Certificate

active

06243307

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device incorporating a tester circuit to test a semiconductor device, particularly a semiconductor memory device. The present invention also relates to the structure of a testing device to test a semiconductor device incorporating such a tester circuit.
2. Description of the Background Art
Most semiconductor memory devices include spare memory cells to allow a defective memory cell, if present, to be replaced with the spare memory cell to repair the defective chip.
FIG. 19
is a schematic block diagram showing a structure of a redundant circuit provided for a memory array unit
8010
of such a semiconductor memory device.
One memory cell in memory array unit
8010
is selected by externally applied row address signals RA
0
-
13
and column address signals CA
0
-
8
. In a write operation, the data applied to a data input/output terminal DQ (not shown) is written into the selected memory cell. In a read out operation, the data read out from memory array unit
8010
is provided to data input/output terminal DQ.
A row decoder
8020
responds to the input row address to select memory cells of one row for a read or write operation. A column decoder
8030
selects one column according to the input column address and further selects one memory cell out of the one row of memory cells selected according to the row address.
In the structure of
FIG. 19
, two spare rows SR
1
and SR
2
, and two spare columns SC
1
and SC
2
are provided as the spare memory cells. Spare row SR
1
is constituted by one row of memory cells SRM
1
and a spare row decoder SRD
1
. Spare row SR
2
is constituted by one row of memory cells SRM
2
and a spare row decoder SRD
2
.
Spare column SC
1
is constituted by one column of memory cells SCM
1
and a spare column decoder SCD
1
. Spare column SC
2
is constituted by one column of memory cells SCM
2
and a spare column decoder SCD
2
.
In spare row decoders SRD
1
and SRD
2
, a row address corresponding to a defective memory cell is recorded in advance. The input row address is compared with the row address corresponding to the defective memory cell. When the row addresses match, a corresponding spare memory cell SRM
1
or SRM
2
is selected. When spare row memory cell SRM
1
or SRM
2
is selected, spare row decoders SRD
1
and SRD
2
control row decoder
8020
so that a memory cell of the normal memory array is not selected.
Similarly, a column address corresponding to a defective memory cell is recorded in advance in spare column decoders SCD
1
and SCD
2
. Spare column decoders SCD
1
and SCD
2
compare the input column address with this recorded column address corresponding to a defective memory cell. When the column addresses match, a corresponding spare column memory cell SCM
1
or SCM
2
is selected. When spare column memory cell SCM
1
or SCM
2
is selected, spare column decoders SCD
1
and SCD
2
control column decoder
8030
so that a memory cell in the normal memory array is not selected.
In the case where there is a defective memory cell in the memory array, that memory cell is replaced by spare rows SR
1
and SR
2
or spare columns SC
1
and SC
2
to repair the defective memory cell. For example, consider the case where there are defective memory cells DBM
1
to DBM
8
in the memory array, as shown in FIG.
19
.
It is assumed that defective memory cells DBM
2
-DBM
4
correspond to the same row address RF
2
, and defective memory cells DBM
3
and DBM
5
-DBM
7
correspond to the same column address CF
3
.
Therefore, by replacing the rows corresponding to row addresses RF
1
and RF
2
in the normal memory array with spare rows SR
1
and SR
2
, and by replacing the columns corresponding to column addresses CF
3
and CF
8
with spare columns SC
1
and SC
2
, memory array
8010
can be repaired.
FIG. 20
is a schematic block diagram showing a structure of a memory tester
9000
.
Memory tester
9000
has a redundancy analysis function to detect a defective memory cell in a semiconductor memory device
8000
and to determine whether semiconductor memory device
8000
can be repaired by replacement with either a spare row or a spare column.
Memory tester
9000
includes a signal generator
9010
, a comparator
9020
, a failure memory
9030
, and an analysis device
9040
.
Signal generator
9010
generates and provides to semiconductor memory device
8000
that is the subject of measurement row address signals RA
0
-
13
, column address signals CA
0
-
8
and write data TD used for testing.
Although not shown, signal generator
9010
also generates other control signals such as a write enable signal WE, a chip select signal /CS, a row address strobe signal /RAS and a column address strobe signal /CAS. which are provided to under-measurement semiconductor memory device
8000
.
Furthermore, signal generator
9010
generates expected value data ED corresponding to write data TD in the read out operation in the test mode. Comparator
9020
compares the data output from semiconductor memory device
8000
with expected value data ED to determine whether under-measurement semiconductor memory device
8000
outputs the proper data. The determination result is output as a pass/fail signal P/F.
Failure memory
9030
includes storage elements identical in number with that of the memory cells in under-measurement semiconductor memory device
8000
.
Failure memory
9030
stores the level of the determination resultant signal P/F output from comparator
9020
in the storage element specified by row address signals RA
0
-
13
and column address signals CA
0
-
8
output from signal generator
9010
.
Analysis device
9040
reads out the data from failure memory
9030
to analyze which of the spare row and the spare column the defective memory should be replaced for repair.
Analysis device
9040
provides the address of the defective memory to be repaired to a repair device, for example, a laser trimmer device. The laser trimmer device programs the value of the defective address by trimming the fuse element provided in semiconductor memory device
8000
. Details of laser trimming is disclosed in, for example, Japanese Patent Laying-Open No. 4-330710.
In a conventional memory tester
9000
, the capacity of failure memory
9030
had to be increased reflecting increase in the memory capacity of under-measurement semiconductor memory device
8000
. Failure memory
9030
is expensive and must allow high speed operation. Therefore, there was a problem that increasing the capacity of failure memory
9030
is costly.
Recently, a semiconductor memory device with a built-in testing device or a semiconductor device incorporating a semiconductor memory device with a built-in testing device are fabricated. The semiconductor device includes a signal generator
9010
to carry out testing without a memory tester. Although detection can be made whether there is a defective memory cell in the memory array in such semiconductor memory devices or semiconductor devices with the built-in testing device, it was difficult to effect a test realizing the redundancy analysis function itself. Redundancy analysis could not be carried out since it is difficult to incorporate in a semiconductor memory device or a semiconductor device a failure memory
9030
that requires a large amount of capacity equal to that of the under-measurement semiconductor memory device or the semiconductor memory device incorporated in a semiconductor device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device or a semiconductor device incorporating a semiconductor memory device with a built-in tester circuit that can detect a defective memory cell and that can replace the defective memory cell with a redundant memory cell.
Another object of the present invention is to provide a testing device that can detect a defective memory cell speedily and that can carry out redundancy analysis with a simple structure even in the case where the memory capacity of the under-measurement semi

Affiliated with

Also associated with

Rating

Semiconductor device including tester circuit suppressible... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device including tester circuit suppressible..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device including tester circuit suppressible... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2523560