Semiconductor memory device capable of generating offset...

Details Semiconductor memory device capable of generating offset... Semiconductor memory device capable of generating offset...

2000-09-14

2001-09-11

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S117000, C365S145000

Reexamination Certificate

active

06288950

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as a ferroelectric random access memory (FeRAM) device, and more particularly, to the improvement of a reliability test or a burn-in test of the semiconductor memory device.
2. Description of the Related Art
In a prior art semiconductor memory device including a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells each connected between one of the word lines and one of the bit lines, and a plurality of sense amplifiers for amplifying the difference in potential between the pair of the bit line a plurality of offset circuits is provided for applying an offset voltage to at least one of the pair of the bit lines to reduce the difference in potential between the pair of the bit lines before the sense amplifiers are operated, thus carrying out a reliability test, i.e., a burn-in test (see: JP-A-11-149796). This will be explained later in detail.
In the above-described prior art semiconductor memory device, however, the offset voltage is greatly dependent upon the voltage at a bit line. As a result, if the offset voltage is too large, some of normal semiconductor memory devices will be deemed to be defective and scrapped. On the other hand, if the offset voltage is too small, some of defective semiconductor memory devices will pass. Thus, it is impossible to carry out a high reliability test.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device capable of carrying out a high reliability test.
According to the present invention, in a semiconductor memory device including a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells each connected between one of the word lines and one of the bit lines, and a plurality of sense amplifiers for amplifying the difference in potential between the pair of the bit lines, a plurality of offset circuits is provided for applying an offset voltage independent of voltages at the bit lines to at least one of the pair of the bit lines, to reduce the difference in potential between the pair of the bit lines before the sense amplifiers are operated.


REFERENCES:
patent: 5237533 (1993-08-01), Papaliolios
patent: 5300824 (1994-04-01), Iyengar
patent: 5991189 (1999-11-01), Miwa
patent: 11-39882 (1999-02-01), None
patent: 11-149796 (1999-06-01), None
European Search Report dated Feb. 5, 2001.

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