Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-11-30
2001-05-22
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S280000, C257S281000, C257S284000, C257S192000, C257S774000, C438S167000, C438S637000, C438S638000, C438S639000, C438S640000
Reexamination Certificate
active
06235626
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a gate electrode of a field effect transistor using an insulating film with an opening pattern for burying a metal material into the opening pattern.
A conventional method of forming a fine and low resistive gate electrode of a ficld effect transistor is disclosed in Japanese laid-open patent publication No. 5-326564 and will be described with reference to
FIGS. 1A through 1G
which are fragmentary cross sectional elevation views illustrative of the conventional method of forming a fine and low resistive gate eletrode of a field effect transistor.
FIG. 1G
is a fragmentary cross sectional elevation view illustrative of a double stage recessed structure field effect transistor formed in the conventional fabrication method. The conventional field effect transistor has a semi-insulating GaAs substrate
21
, a GaAs buffer layer
22
provided on the semi-insulating GaAs substrate
21
, a first n-GaAs layer
23
a
provided on the GaAs buffer layer
22
, a first n-AlGaAs layer
24
a
provided on the first n-GaAs layer
23
a
, a second n-GaAs layer
23
b
provided on the first n-AlGaAs layer
24
a
, a second n-AlGaAs layer
24
b
provided on the second n-GaAs layer
23
b
, n+-GaAs layers
25
provided on a predetermined region, except for a gate region, of said second n-AlGaAs layer
24
b
, silicon dioxide side walls
28
provided on selected regions in the gate region, except for a center region thereof, a Ti/Pt/Au gate electrode film
29
provided on the center region in the gate region and also over the silicon dioxide side walls
28
, and AuGe/Ni/Au ohmic contacts
30
on the Ti/Pt/Au gate electrode film
29
and the n+-GaAs layers
25
. The Ti/Pt/Au gate electrode film
29
has a bottom portion which is provided within a recessed portion formed in the first n-GaAs layer
23
a.
With reference to
FIG. 1A
, the GaAs buffer layer
22
is formed on the semi-insulating GaAs substrate
21
. The first n-GaAs layer
23
a
is formed on the GaAs buffer layer
22
. The first n-AlGaAs layer
24
a
is formed on the first n-GaAs layer
23
a
. The second n-GaAs layer
23
b
is formed on the first n-AlGaAs layer
24
a
. The second n-AlGaAs layer
24
b
is formed on the second n-GaAs layer
23
b
. The n+-GaAs layers
25
is formed on a predetermined region, except for a gate region, of the second n-AlGaAs layer
24
b
. A silicon oxide nitride film SiON
26
having a thickness of 2000 angstroms is then formed on the n+-GaAs layers
25
.
With reference to FIG. lB, a photo-resist film
27
is applied on the silicon oxide nitride film SiON
26
and then an opening pattern having a 0.5 micrometers size is formed in the photo-resist film
27
so that the opening pattern is positioned over a predetermined gate region for forming a gate electrode. The photo-resist pattern
27
is used as an etching mask for reaction ion etching to the silicon oxide nitride film SiON
26
, the n+-GaAs layers
25
and the second n-AlGaAs layer
24
b
to form a recessed portion.
With reference to
FIG. 1C
, after the used photo-resist pattern
27
is removed, a plasma enhanced chemical vapor deposition method is carried out to deposit a silicon dioxide film having a thickness of 4000 angstroms for subsequent reaction ion etching to the deposited silicon dioxide film, whereby silicon dioxide side walls
28
are formed which have a width of about 0.2 micrometers within the recessed portion, wherein a center region of the second n-GaAs layer
23
b
is not covered with the silicon dioxide side walls
28
and shown through the recessed portion.
With reference to
FIG. 1D
, a wet etching process to the second n-GaAs layer
23
b
and the first n-AlGaAs layer
24
a
is carried out to form an under-cut recessed portion which extends under the silicon dioxide side walls
28
.
With reference to
FIG. 1E
, a Ti/Pt/Au gate electrode film
29
is entirely deposited which extends on the center region of the first n-GaAs layer
23
a
and over the silicon dioxide side walls
28
as well as over the silicon oxide nitride film SiON
26
.
With reference to
FIG. 1F
, the Ti/Pt/Au gate electrode film
29
is selectively etched by an ion-milling process to remain on the center region of the first n-GaAs layer
23
a
and over the silicon dioxide side walls
28
as well as over adjacent portions the silicon oxide nitride film SiON
26
to the silicon dioxide side walls
28
.
With reference to
FIG. 1G
, the silicon oxide nitride film SiON
26
is removed. The Ti/Pt/Au gate electrode film
29
is used as a mask for deposition of AuGe/Ni/Au ohmic contacts
30
which extend over the Ti/Pt/Au gate electrode flm
29
and the n+-GaAs layers
25
except under upper-extending portions of the Ti/Pt/Au gate electrode film
29
.
The required scaling down of the gate length can be obtained by conditions for forming photo-resist patterns
27
, the ion reactive etching conditions to the silicon oxide nitride film SiON
26
, the n+-GaAs layers
25
and the second n-AlGaAs layer
24
as well as deposition conditions to the silicon dioxide side walls
28
.
The conventional method described above is disadvantageous as requiring complicated processes and highly accurate controls to opening size of opening, the thickness of the side wall Elm, the etching amount. Variations in size of the opening pattern of the photo-resist film cases variation in size of the recessed portion, resulting in enlarged variation in gate length of the gate electrode.
In the above circumstances, it had been required to develop a novel method of forming a gate electrode of a field effect transistor using an insulating film with an opening pattern free from the above disadvantages.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel method of forming a gate electrode of a field effect transistor using an insulating film with an opening pattern free from the above problems.
It is a further object of the present invention to provide a novel method of forming a gate electrode free of any variation in gate length.
It is a still further object of the present invention to provide a novel method of forming a gate electrode with reduced number of processes.
The present invention provides a method of forming a gate recess in an insulating film on a substrate for depositing a gate electrode film being in contact with a part of the substrate and also extending at least within the gate recess. The method comprises the steps of: forming an etching mask pattern with a first opening pattern on the insulating film; carrying out a first anisotropic etching process by use of the etching mask pattern at a first selective ratio of the etching mask pattern to the insulating film, thereby to form a first recessed portion having a bottom which lies at a fist level higher than an interface level between the insulating film and the substrate; and carrying out a second anisotropic etching process by use of the etching mask pattern again at a second selective ratio of the etching mask pattern to the insulating film, wherein the second selective ratio is higher than the first selective ratio, thereby to form a gate recess which comprises a second recessed portion both having a bottom which lies at the interface level and having first side walls of a first oblique angle and a third recessed portion both having a bottom united with a top of the second recessed portion and having second side walls of a second oblique angle which is smaller than the first oblique angle.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
REFERENCES:
patent: 4377899 (1983-03-01), Otani et al.
patent: 5362677 (1994-11-01), Sakamoto
patent: 5391899 (1995-02-01), Kohno
patent: 5444022 (1995-08-01), Gardner
patent: 5457070 (1995-10-01), Hirade
patent: 5880860 (1999-03-01), Kohno
patent: 5899746 (1999-05-01), Mukai
patent: 6127734 (2000-10-01), Kimura
patent: 64-7572 (1989-01-01), None
patent: 2-238636 (199
Makino Yoichi
Miyamoto Hironobu
Keshavan Belur
NEC Corporation
Smith Matthew
Young & Thompson
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