Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-01
2001-07-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S626000, C438S627000, C438S639000, C438S786000, C438S787000, C438S791000
Reexamination Certificate
active
06258712
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87121964, filed Dec. 31, 1998.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a borderless contact.
2. Description of the Related Art
As the integration density of semiconductor devices increases, more circuit elements must to be packed in a unit surface area of the device substrate, and circuit elements such as interconnects are necessarily increased between MOS transistors of the IC device. In many highly integrated semiconductor devices, more than two levels of interconnecting metal layers are demanded, called multilevel metal interconnects (MLM).
In the conventional method, a landed contact with a contact window width that is less than the conductive line width is provided for preventing misalignment and to insure the connection between the contact and conductive line. The landed contact must use a larger surface area of the device substrate, so that it is difficult to enhance the integration density of semiconductor devices and the capital expenditure increases. As the integration of semiconductor devices is increased, instead of the landed contact, another conventional method for forming a borderless contact is provided. A borderless contact for which the conductive line width is substantially the same as the contact window width has been used in current semiconductor fabrication process in order to downsize the semiconductor devices. However, the over-etching due to misalignment leads to an inability of contact window to connect completely with the conductive line.
As semiconductor device integration continuously increases, device dimensions are necessarily accordingly reduced. Thus, a contact window in the device needs a more precise alignment to prevent an improper electrical coupling to the adjacent device element from occurring as a metallic material is filled into the contact window. The improper electrical coupling usually causes a short circuit in the device. For example, a contact window is desired to expose an interchangeable source/drain region but it may also expose a portion of a gate structure if a misalignment occurs. When the misalignment contact window is filled with metallic material, the interchangeable source/drain and the gate structure are improperly coupled, resulting in a short circuit. In order to enhance the process window and prevent a short circuit from occurring, a self-alignment contact technology is developed.
FIG. 1A
is schematic, cross-sectional view showing a standard borderless contact. As shown in
FIG. 1A
, a plurality of conductive lines
102
are formed on a substrate
100
, and the conductive lines
102
comprise a titanium/aluminum copper/titanium/titanium nitride multi-layer structure. The conductive lines
102
and the substrate
100
are covered by an inter-metal dielectric layer
104
; the inter-metal dielectric layer
104
is made of silicon oxide. The inter-metal dielectric layer
104
covering the conductive lines
102
is removed by photolithography and etching to form a plurality of contact windows
106
and expose the conductive lines
102
. A liner
108
, made from titanium nitride, is formed as a diffusion barrier layer conformal to the substrate
100
. Then, the contact windows
106
are filled with a conductive layer
110
made from tungsten.
FIG. 1B
is schematic, cross-sectional view showing a worst case misalignment in a currently used borderless contact. As shown in
FIG. 1B
, a borderless contact process is performed to form a plurality of contact windows
106
that exposes only the conductive lines
102
on the substrate
100
. However, once a misalignment occurs, the occurrence of over-etching due to misalignment is generated; not only the conductive lines
102
on the substrate
100
are exposed, but also the substrate
100
surface is exposed by the contact windows
106
. If misalignment occurs in a conventional borderless contact process, the over-etching of contact formation etches through the inter-metal dielectric layer without obstruction. If the substrate
100
has completed the front end process before the step of forming the contact windows
106
, the contact windows
106
in contact with the substrate
100
cause the resistance-capacitance (RC) of devices to increase, so that the device performance is reduced. Additionally, the occurrence of over-etching due to misalignment results in a leakage current, and therefore the yield is decreased.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a method for a self-aligniment process to enhance the yield of borderless contact. The method can improve the resistance-capacitance (RC) and avoid the leakage current.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for a self-alignment process to enhance the yield of borderless contact. A substrate is provided, a plurality of conductive lines are formed on the substrate. A first inter-metal dielectric layer is formed over the substrate; the surface level of the first inter-metal dielectric layer located between the conductive lines is substantially the same as the surface level of the conductive lines. A first barrier layer is formed on the conductive lines and the first inter-metal dielectric layer, wherein the each of the conductive lines has a second barrier layer formed thereon. A second inter-metal dielectric layer is formed on the first barrier layer, the second inter-metal dielectric layer is patterned to form an opening. The first barrier layer and the second barrier layer on the bottom of the opening are removed to expose the conductive lines. A liner is formed conformal to the substrate, and a conductive layer is formed over the substrate and within the opening.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5565529 (1996-10-01), Babich
patent: 5834845 (1998-11-01), Stolmeijer
patent: 6020258 (2000-02-01), Yew et al.
patent: 6054380 (2000-04-01), Naik
Huang Jiawei
J.C. Patents
Nguyen Ha Tran
Niebling John F.
Taiwan Semiconductor Manufacturing Co. Ltd.
LandOfFree
Method for forming a borderless contact does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a borderless contact, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a borderless contact will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2522202