Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-02-06
2001-06-12
Pham, Long (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S758000
Reexamination Certificate
active
06246085
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor device having a through-hole of a two-level structure and, more particularly, to an electrode structure for a stacked capacitor of a memory cell in a semiconductor memory device.
(b) Description of the Related Art
Dynamic random access memory (DRAM) has a stacked capacitor in each memory cell for storing data thereon.
FIG. 1
shows the structure of a stacked capacitor in a conventional memory cell, which is fabricated by a known process as described below. First, a field oxide film
102
of an about 400 nm thickness is formed by a LOCOS technology on a p-conductivity type silicon substrate
101
to define an array of cell areas. Subsequently, a gate oxide film (not shown), gate electrode (not shown) and source/drain regions
103
of a MOSFET are formed in each cell area, followed by deposition of a BPSG (borophospho-silicate glass) film
104
as an interlevel dielectric film having a thickness of about 1000 nm and deposition of a SiO
2
film
105
having a thickness of about 200 nm. Thereafter, a through-hole
106
of a 0.3 &mgr;m×0.3 &mgr;m cross-section is formed in the BPSG film
104
and the SiO
2
film
105
in each cell region to expose a part of the source/drain region
103
. Then, a phosphorous (P)-doped amorphous silicon
107
is deposited on the entire surface including inside the through-hole
106
to a thickness of about 500 nm, followed by patterning thereof to form a capacitor electrode, or bottom electrode of a stacked capacitor.
In the design of the cell structure as described above, the alignment margin between the through-hole
106
and the bottom electrode
107
has been reduced down to as low as 0.05 &mgr;m with the development of a higher integration of the DRAM. In
FIG. 1
, there is shown an ideal case of the alignment wherein no misalignment is present between the through-hole
106
and the bottom electrode
107
. However, a critical misalignment is sometimes involved in the DRAM, as shown in
FIG. 2A
, wherein the misalignment is larger than the design margin L
1
. In such a case, the bottom electrode
107
exposes the SiO
2
film
105
and the BPSG film
104
within the through-hole
106
.
Back to
FIG. 1
, the patterning of the bottom electrode
107
is generally followed by a pre-treatment in which a natural oxide film is removed from the surface of the bottom electrode
107
by using a dilute hydrof luoric acid before the subsequent step of deposition of a nitride film acting as a capacitor film, or insulator film of the capacitor. In this step, the etching rate by the dilute hydrofluoric acid is as low as about 200 angstroms/minute in the SiO
2
film as compared to about 600 angstroms/minute in the BPSG film.
In addition, it takes above five minutes to entirely remove the natural oxide film by the etching, and accordingly, as shown in
FIG. 2B
, the BPSG film
104
is additionally etched by a significant amount in the through-hole
106
. Similar problem occurs in the step of formation of a hemispherical grain (HSG) structure for the capacitor electrode. In the process for fabrication of the HSG structure, the etching step for natural oxide film is generally effected on the capacitor electrode by using a dilute hydrof luoric acid, which also involves a situation similar to etching of the BPSG film.
To overcome the above problem, it is proposed that an oxide spacer film be formed on the side wall of the through-hole for protection of the BPSG film, as shown in FIG.
3
A. In this proposal, a SiO
2
film
108
a
as low as about 100 nm-thick is formed after the through-hole
106
is formed in a SiO
2
film
105
and the BPSG film
104
for exposing the surface of the source/drain region
103
. The SiO
2
film
108
a
is then etched-back to be left in the through-hole
106
as a side-wall film
108
, followed by deposition of a P-doped amorphous silicon layer to a thickness of about 500 nm and patterning thereof to form a bottom electrode
107
in the through-hole
106
, as shown in FIG.
3
B. In this technique, the alignment margin L
1
between the through-hole
106
and the bottom electrode
107
is increased by an amount corresponding to the thickness (0.1 &mgr;m) of the side wall
108
, thereby avoiding the etching of the BPSG film
104
even if a significant misalignment occurs between the bottom electrode
107
and the through-hole
106
.
In the proposal as mentioned above, however, the side-wall film
108
generally suffers from a poor step coverage problem and variation of the film thickness of the side wall due to the high aspect ratio of the through-hole
106
in a higher integrated circuit. The poor step coverage and the variation of the film thickness necessitates a marginal etching of the side-wall film for exposing the silicon surface, which sometimes involves an over-etching of the silicon surface as illustrated in
FIG. 3B
to cause a leakage current at the junction in the silicon substrate
101
.
Patent Publication JP-A-2(1990)-170561 describes a similar technique wherein two-level interconnection system has a side-wall film in a through-hole which connects upper and lower level interconnect layers together.
Patent Publication JP-A-3-174766 proposes an improvement of the aspect ratio, such as shown in
FIG. 4
, by providing a two-layer insulation structure, wherein two through-holes for receiving a polysilicon plug
205
and a polysilicon electrodes
208
and formed in SiO
2
films
204
and
206
, respectively, are communicated to each other to define a substantially single capacitor electrode.
In the described two-layer insulation structure, although the aspect ratio of the through-hole can be improved, the alignment margin between the capacitor electrode and the through-hole cannot be improved. Moreover, it raises costs of the memory device due to the increased fabrication step for photolithography.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of improving the step coverage of an insulator film in the through-hole to obtain a controlled thickness for a side-wall film in the through-hole, without involving an over-etching of a substrate.
The present invention provides a semiconductor device comprising a semiconductor substrate, a first conductive layer overlying or formed in the semiconductor substrate, a insulator film formed on the first conductive layer and having therein a through-hole for exposing a part of the first conductive layer, a conductive plug disposed in contact with the part of the first conductive layer and filling a first portion of the through-hole, a side-wall film formed on an inner wall of a remaining portion of the through-hole, and a second conductive layer formed on the insulator film and the side-wall film to be connected to the first conductive layer through the conductive plug.
In accordance with the semiconductor device of the present invention, the step coverage of an insulator film for the side-wall film can be improved by providing the conductive plug in the first portion of the through-hole for reducing the effective aspect ratio of the through-hole, without increasing the photolithographic step. The conductive plug also removes occurrence of an over-etching of the semiconductor substrate during the etch-back of the insulator film for forming the side-wall film, in case that the first conductive layer is a diffused region of the semiconductor substrate.
REFERENCES:
patent: 5451539 (1995-09-01), Ryou
patent: 5478768 (1995-12-01), Iwasa
patent: 5532956 (1996-07-01), Watanabe
patent: 5701647 (1997-12-01), Saenger et al.
patent: 5789030 (1998-08-01), Rolfson
patent: 5808855 (1998-09-01), Chan et al.
patent: 5825059 (1998-10-01), Kuroda
patent: 6005268 (1999-12-01), Parekh et al.
patent: 2-170561 (1990-07-01), None
patent: 3-174766 (1991-07-01), None
patent: 6-89941 (1994-03-01), None
patent: 7-30077 (1995-01-01), None
patent: 8-274278 (1996-10-01), None
Coleman William David
NEC Corporation
Pham Long
Young & Thompson
LandOfFree
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