Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-30
2001-09-04
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S654000, C438S656000
Reexamination Certificate
active
06284653
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to form semiconductor devices, and more specifically to a method used to form a composite structure comprised of a barrier layer on an underlying metal silicide layer, with the composite structure located at the bottom of a contact hole opening, and formed prior to formation of a metal plug structure in the contact hole opening.
(2) Description of Prior Art
The use of metal silicide layers on specific semiconductor conductive regions, such as gate structures, or source/drain regions, have resulted in decreased word line, and bit line resistance, allowing increased metal oxide semiconductor field effect transistor (MOSFET), device performance to be realized. The formation of metal silicide layers can in most cases be performed using self-alignment procedure, in which a metal layer is blanket deposited, then annealed to form the desired metal silicide layer on regions in which the metal layer resided on underlying conductive regions such as on polysilicon gate structures, and on silicon source/drain regions, located adjacent to the polysilicon gate structure. Unreacted metal, located on non-conductive regions, such as insulator spacers on the sides of the polysilicon gate structure, is then selectively removed resulting in the metal silicide layers, self aligned on underlying conductive regions.
The metal layer, used for metal silicide, is usually obtained via plasma vapor deposition (PVD), procedures, conformally deposited on the non-severe topographies offered by gate structures and adjacent source/drain regions. However in some cases metal silicide layers have to be formed on conductive regions located at the bottom of high aspect ratio contact holes. The narrow diameter, and depth of the high aspect ratio contact hole, present a difficult topography for the PVD metal to contour. The ability to deposit the desired thickness of metal on the conductive region exposed at the bottom of the high aspect ratio contact hole can however be increased via use of a more directional metal deposition procedure. Therefore this invention will describe a method of directionally depositing a metal layer on a conductive region located at the bottom of a high aspect ratio contact hole, excluding deposition on the sides of the high aspect ratio contact hole. Subsequent anneal cycles, performed in specific ambients, result in the formation of the desired metal silicide layer on the underlying conductive region, and result in the selective formation of the desired a barrier layer, located on the newly formed metal silicide layer. Prior art such as Lee et al, in U.S. Pat. No. 5,552,340, describe a method of forming a barrier layer on an underlying metal silicide layer, which is located on a conductive region exposed at the bottom of a contact hole opening. However that prior art, unlike the present invention in which the barrier layer is selectively formed only on metal silicide layers, deposits the barrier layer, resulting in barrier layer located on the sides of the contact hole, thus decreasing the space available in the contact hole for a subsequent conductive plug structure.
SUMMARY OF THE INVENTION
It is an object of this invention to form a metal silicide layer on a portion of a conductive region in a semiconductor substrate, exposed in a high aspect ratio contact hole, then to selectively form a barrier layer on the metal silicide, via an anneal procedure performed in a nitrogen containing ambient.
It is another object of this invention to supply the metal, for the metal silicide layer, using a ion metal plasma (IMP), procedure, resulting in metal ions being deposited only on the top surface of the conductive region exposed in the high aspect ratio contact hole, and only on the top surface of the insulator layer in which the high aspect ratio contact hole was defined in, without deposition of metal ions on the sides of the high aspect ratio contact hole.
It is still another object of this invention to deposit metal ions via an IMP procedure, only on the top surface of the conductive region exposed in the high aspect ratio contact hole, and only on the top surface of the photoresist shape, used to define the high aspect ratio contact hole, and after selective formation of a barrier layer, remove the unwanted regions of barrier layer from the top surface of the photoresist shape via a lift-off process.
In accordance with the present invention a method of forming a metal silicide layer on a portion of conductive region exposed at the bottom of a high aspect ratio contact hole, followed by selective formation of a barrier layer, on the underlying metal silicide layer, is described. A first iteration entails deposition of metal layer, comprised of metal ions, obtained via an anisotropic, ion metal plasma (IMP), procedure, with the metal ion layer deposited only on the portion of conductive region exposed at the bottom of a high aspect ratio contact, and only on the top surface of the insulator layer in which the high aspect ratio contact hole was defined in. After a first anneal cycle, used to form a metal silicide layer on the exposed conductive region, the unreacted, metal ion layer is selectively removed from the top surface of insulator layer. A second anneal procedure is next performed in a nitrogen containing ambient to convert a top portion of the metal silicide layer to a barrier layer. A conductive plug structure is then formed, filling the high aspect ratio contact hole, and overlying the barrier layer-metal silicide structure, in the high aspect ratio contact hole.
A second iteration features the deposition of the metal ion layer, via the anisotropic IMP procedure, on the portion of conductive region exposed at the bottom of the high aspect ratio contact hole, and on the top surface of the photoresist shape used to define the high aspect ratio contact hole, in an underlying insulator layer. After removal of the photoresist shape, including the lifting off of the metal ion layer on the top surface of the photoresist shape, a first anneal cycle is performed to create a metal silicide layer on the exposed conductive region, consuming the entire metal ion layer previously located on the conductive region. A second anneal procedure, performed in a nitrogen containing ambient, converts a top portion of the metal silicide layer, located on the conductive region, to a barrier layer, resulting in a composite structure of a barrier layer-metal silicide layer, located on the portion of the conductive region exposed at the bottom of the high aspect ratio contact hole. A conductive plug structure is again formed, filling the high aspect ratio contact hole, and overlying the barrier layer-metal silicide structure, in the high aspect ratio contact hole.
REFERENCES:
patent: 5552340 (1996-09-01), Lee et al.
patent: 5571572 (1996-11-01), Snadhu et al.
patent: 5882399 (1999-03-01), Ngan et al.
patent: 5962933 (1999-10-01), Xu et al.
patent: 5966607 (1999-10-01), Chee et al.
patent: 5985789 (1999-11-01), Kim et al.
patent: 6025274 (2000-02-01), Lin et al.
patent: 6054379 (2000-04-01), Yan et al.
patent: 6140241 (2000-10-01), Shue et al.
Ackerman Stephen B.
Lebentritt Michael
Saile George O.
Vanguard International Semiconductor Corp.
LandOfFree
Method of selectively forming a barrier layer from a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of selectively forming a barrier layer from a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of selectively forming a barrier layer from a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2521707