Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1998-06-05
2001-08-07
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
Reexamination Certificate
active
06271062
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin-film semiconductor device and a method for fabricating the same. More specifically, the present invention relates to a thin-film semiconductor device, such as a thin-film transistor, applicable to a liquid crystal display device using a thin-film transistor (TFT-LCD), and a method for fabricating the same.
2. Description of the Related Art
A conventional thin-film semiconductor device will be described by illustrating a thin-film transistor (hereinafter, simply referred to as a TFT) as an example. In addition, a method for producing a conventional TFT will be described by reference to
FIGS. 20 and 21
.
FIG. 20
is a cross-sectional view of a conventional TFT
2000
having a reversed stagger structure. The TFT
2000
includes: a gate electrode
2002
; a gate insulating film
2003
; an intrinsic amorphous silicon (an i-type a-Si) thin film
2004
; a channel protection film
2005
; and an n-type amorphous silicon (an n-type a-Si) thin film
2006
consisting a source region
2006
a
and a drain region
2006
b.
These films are formed in this order on an insulating substrate
2001
. A source electrode
2007
a
and a drain electrode
2007
b
are respectively formed on a predetermined region of the source region
2006
a
and the drain region
2006
b
of the n-type a-Si thin film
2006
. A pixel electrode
2008
connected to either the source electrode
2007
a
or the drain electrode
2007
b
is further formed on one of the electrodes
2007
a
and
2007
b.
In this conventional TFT
2000
shown in
FIG. 20
, the n-type a-Si thin film
2006
is formed by a plasma chemical vapor deposition (P-CVD) method so as to cover the channel protection film
2005
. Thereafter, the n-type a-Si thin film
2006
is patterned in a predetermined shape as shown in FIG.
20
.
A TFT having a similar structure to that shown in
FIG. 20
is disclosed in Japanese Laid-Open Patent Publication Nos. 59-141271, 61-59873, and 60-98680. In the TFT disclosed in these patient publications, a microcrystalline silicon (&mgr;c-Si) thin film is used. Japanese Laid-Open Patent Publication No. 59-141271 discloses a TFT in which a gate insulating film has a double-layered structure consisting of a film formed by anodizing a metallic film which is used as a gate electrode and an insulating film formed by a P-CVD method, and a &mgr;c-Si film which is used as a semiconductor layer.
Japanese Laid-Open Patent Publication No. 61-59873 discloses a TFT having a reversed stagger structure in which a double-layered semiconductor layer is used as an i-type semiconductor layer. The semiconductor layer having the double-layered structure consists of an a-Si film provided as a first layer in order to prevent the damage caused by the glow-discharge of high power and a &mgr;c-Si film provided as a second layer in order to improve field effect mobility. However, a channel portion of the TFT is formed in the a-Si film. Therefore, even if the structure disclosed in this patent publication is used, it is also difficult to improve field-effect mobility. In addition, since the thickness of the second layer, i.e., the &mgr;c-Si film, is required to be 100 nm, the throughput is reduced. This is because the deposition of the &mgr;c-Si film with a thickness of 100 nm is required to be performed for about 2000 seconds in the case of using a typical deposition rate.
Japanese Laid-Open Patent Publication No. 60-98680 discloses a TFT in which an i-type semiconductor layer has a double-layered structure consisting of a &mgr;c-Si film with a thickness of 15 nm or less as a first layer and an amorphous semiconductor layer having an energy gap larger than that of the first layer as a second layer. In this structure, the throughput is also reduced. Moreover, since other materials are added to the semiconductor film having a larger band gap, it is difficult to obtain a semiconductor film of a satisfactory quality and improve the field-effect mobility.
FIG. 21
is a cross-sectional showing another conventional TFT
2100
having a reversed stagger structure. The TFT
2100
shown in
FIG. 21
includes: a gate electrode
2102
; a gate insulating film
2103
; and intrinsic semiconductor thin film
2104
; a channel protection film
2105
; and an n-type semiconductor layer
2106
consisting of a source region
2106
a
and a drain region
2106
b.
These films are formed in this order on an insulating substrate
2101
. A source electrode
2107
a
and a drain electrode
2107
b
are respectively formed so as to partially cover the predetermined portion of the source region
2106
a
and the drain region
2106
b
of the n-type semiconductor layer
2106
. A pixel electrode
2108
connected to either the source electrode
2107
a
or the drain electrode
2107
b
is further formed on one of the electrodes
2107
a
and
2107
b.
In the TFT
2100
shown in
FIG. 21
, the n-type semiconductor layer
2106
is formed by discharge decomposing a gas containing an impurity such as hydrogen-diluted phosphine so as to generate ions, and implanting the ions into an intrinsic semiconductor thin film
2104
formed on the gate insulating film
2103
by using the channel protection film
2105
as a mask while applying an acceleration thereto.
In the case of fabricating the TFT shown in
FIG. 20
, the following problems occur. First, in order to form the n-type a-Si thin film
2006
, it is necessary to perform additional process steps of depositing the n-type a-Si thin film
2006
by the P-CVD method so as to cover the channel protection film
2005
and patterning the n-type a-Si thin film
2006
so as to partially overlap with the channel protection film
2005
. As a result, the number of the necessary process steps increases. In addition, in positioning a part of the n-type a-Si thin film
2006
on the channel protection film
2005
, some margin of error is required, so that the channel length becomes disadvantageously longer and the amount of the ON current of the TFT
2000
is reduced.
In addition, since the field-effect mobility of the i-type a-Si film is small in the TFT
2000
shown in
FIG. 20
, the channel width can not be reduced in order to secure a sufficient amount of ON current, and it is difficult to downsize the TFT
2000
. Therefore, in a liquid crystal panel using the TFT
2000
shown in
FIG. 20
, it is difficult to increase an opening ratio of the liquid crystal panel. As a result, in the case of using the TFT
2000
, it is necessary to consume a larger amount of power of a back light in order to increase the brightness of a liquid crystal display.
Furthermore, when the TFT
2000
shown in
FIG. 20
is seen from above, some overlapping region exists between the drain electrode
2007
b
and the gate electrode
2002
. As a result, a parasitic capacitance is generated in the overlapping region and considerably affects the display quality. Moreover, the quality of the TFT becomes inferior because of the existence of the residual dust on the insulating substrate
2001
during the deposition of the n-type a-Si thin film
2006
, and the like, thereby adversely reducing the production yield of the TFT.
In fabricating the TFT
2100
shown in
FIG. 21
, as disclosed in Japanese Patent Publications Nos. 1-32661 and 4-54375, the n-type semiconductor layer
2106
including the source region
2106
a
and the drain region
2106
b
is formed by implanting the impurity ions into the intrinsic silicon semiconductor thin film
2104
. Accordingly, the inferiority of the TFT generated during the deposition of the n-type a-Si thin film by the P-CVD method as described in connection with the TFT
2000
shown in
FIG. 20
can be eliminated, and the reduction in the production yield can be prevented. In addition, in the TFT
2100
shown in
FIG. 21
, no overlapping portion exists between the channel protection film
2105
and the n-type semiconductor film
2106
. Thus the channel length can be reduced without any need for considering a margin of error for positioning the channel protection film
2105
Ayukawa Michiteru
Date Masahiro
Fujihara Masaki
Itoga Takashi
Matsuo Takuya
Coleman William David
Nixon & Vanderhye P.C.
Pham Long
Sharp Kabushiki Kaisha
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