Semiconductor memory device having redundancy unit for data...

Details Semiconductor memory device having redundancy unit for data... Semiconductor memory device having redundancy unit for data...

2000-01-10

2001-07-31

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S210130

Reexamination Certificate

active

06269033

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor memory devices and, more particularly, to a semiconductor memory device having a redundancy unit for data line compensation.
Generally, conventional semiconductor memory devices, such as a synchronous dynamic random access memory (SDRAM), include a redundancy unit that uses a shift redundancy system.
FIG. 1
is a circuit diagram of a conventional redundancy unit
100
that uses a shift redundancy system.
As shown in
FIG. 1
, the redundancy unit
100
comprises sixteen data bus lines DB
0
to DB
15
, and a single redundancy data bus line DBs provided for the data bus lines DB
0
to DB
15
. The first to sixteenth data bus lines DB
0
to DB
15
are connected to first to sixteenth input/output data lines DL
0
to DL
15
through related first to sixteenth shift switches SW
0
to SW
15
, respectively. Sense buffers SB
0
to SB
15
and write amplifiers WA
0
to WA
15
are connected between the first to sixteenth shift switches SW
0
to SW
15
and the first to sixteenth input/output data lines DL
0
to DL
15
, respectively.
The first to fifteenth shift switches SW
0
to SW
14
switch the connection of the first to fifteenth input/output data lines DL
0
to DL
14
between the first to fifteenth data bus lines DB
0
to DB
14
and the second to sixteenth data bus lines DL
1
to DB
15
, each of which is one bit higher than each of the first to fifteenth data bus lines DB
0
to DB
14
. The sixteenth shift switch SW
15
switches the connection of the sixteenth input/output data line DL
15
between the sixteenth data bus line DB
15
and the redundancy data bus line DBs.
For example, when a defect occurs at the fourteenth data bus line DB
13
, the shift redundancy operation is performed using the shift switches SW
13
, SW
14
and SW
15
. More specifically, the connection of the fourteenth input/output data line DL
13
is switched to the fifteenth data bus line DB
14
, the connection of the fifteenth input/output data line DL
14
is switched to the sixteenth data bus line DB
15
, and the connection of the sixteenth input/output data line DL
15
is switched to the redundancy data bus line DBs.
That is, in the shift redundancy system, the connection of both of a defective one and the rest of the data bus lines DB
0
to DB
15
is switched, using the related shift switches SW
0
to SW
15
, to the normal upper rank data bus lines DB
0
to DB
15
and to the redundancy data bus line DBs, sequentially. As a result, a semiconductor memory device that functions normally is implemented.
By the way, in the conventional shift redundancy system, the shift switches SW
0
to SW
15
are closer to bit lines BL than the sense buffers SB
0
to SB
15
and the write amplifiers WA
0
to WA
15
, respectively.
During a read operation, data read from memory cells (not shown) has a very small amplitude until it reaches the sense buffers SB
0
to SB
15
via sense amplifiers SA. When the sense buffers SB
0
to SB
15
amplify the data whose amplitude is very small, the ON resistance and parasitic capacitance of the shift switches SW
0
to SW
15
are added to the load on the data bus lines DB
0
to DB
15
and DBs, and thus the bus logic of the sense buffers SB
0
to SB
15
is hard to invert. The same problem is encountered by the write amplifiers WA
0
to WA
15
during a write operation.
In order to make the logic inversion easier, there is a technique in which the size of the shift switches SW
0
to SW
15
is increased so that the effects of the ON resistance and parasitic capacitance of the shift switches SW
0
to SW
15
is reduced. However, larger shift switches SW
0
to SW
15
bring about another problem in that the circuit area is increased and thus it becomes difficult to lay out the switches SW
0
to SW
15
within a pitch of the data bus. Further, another problem is that the power consumption of the semiconductor memory device increases.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device having a redundancy unit that uses the shift redundancy system and generates correct data with high accuracy.
In one aspect of the present invention, a semiconductor memory device including a plurality of input/output data line pairs, a plurality of data bus line pairs corresponding to the plurality of input/output data line pairs, and a redundancy data bus line pair adjacent to one of the plurality of data bus line pairs is provided. Each of a plurality of sense buffers is connected between a corresponding one of the data bus line pairs and between the redundancy data bus line pair. Each of plurality of write amplifiers is connected between a corresponding one of the data bus line pairs and between the redundancy data bus line pair. Each of a plurality of redundancy shift switches selectively connects a corresponding one of the input/output data line pairs to a corresponding one of the data bus line pairs and to one data bus line pair, including the redundancy data bus line pair, adjacent to the corresponding data bus line pair. The plurality of redundancy shift switches are arranged closer to the plurality of input/output data line pairs than the plurality of the sense buffers and the write amplifiers.
In another aspect of the present invention, a semiconductor memory device including a plurality of input/output data line pair groups, including first and second input/output data line pair groups, a plurality of data bus line groups, including first and second data bus line pair groups corresponding to the first and second input/output data line pair groups, respectively, and a redundancy data bus line pair adjacent to one of the plurality of data bus line groups is provided. A plurality of sense buffer groups includes first and second sense buffer groups corresponding to the first and second data bus line pair groups, respectively. Each of the first and second sense buffer groups includes a plurality of sense buffers, each being connected between a corresponding one of the data bus line pairs. A redundancy sense buffer is connected between the redundancy data bus line pair. A plurality of write amplifier groups includes first and second write amplifier groups corresponding to the first and second data bus line pair groups, respectively. Each of the first and second write amplifier groups includes a plurality of write amplifiers, each being connected between a corresponding one of the data bus line pairs, for receiving a mask signal. A redundancy write amplifier is connected between the redundancy data bus line pair. A plurality of redundancy shift switch groups includes first and second redundancy shift switch groups which connect the first and second input/output data line pair groups to the first and second data bus line pair groups and the redundancy data bus line pair. The first and second redundancy shift switch groups are provided closer to the input/output data line pairs than the sense buffers and the write amplifiers. Each of the first and second redundancy shift switch groups includes a plurality of redundancy shift switches, each being connected to a corresponding one of the data bus line pairs and one data bus line pair, including the redundancy data bus line pair, adjacent to the corresponding data bus line pair. A mask signal switching circuit receives a mask signal and provides a switching signal to at least one of the write amplifier and the sense buffer corresponding to one data bus line pair of the second data bus line pair group which is connected to one redundancy shift switch of the first redundancy shift switch group.
In yet another aspect of the present invention, a semiconductor memory device including a plurality of mask groups including first and second mask groups. Each of the first and second mask groups includes a plurality of input/output data line pairs, a plurality of data bus line pairs corresponding to the plurality of input/output data line pairs, amd a redundancy data bus line pair adjacent to one of the plurality of data bus line pairs. Each of a plurality of sense b

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