Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-20
2001-04-24
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S629000, C438S643000, C438S648000, C438S653000, C438S656000, C438S685000, C438S687000
Reexamination Certificate
active
06221757
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor device and in particular to a metal diffusion barrier for electrical interconnections.
A semiconductor device commonly comprises a semiconductor substrate with a plurality of active areas on its surface and multiple metallization layers on top of that surface. The metallization layers are mutually separated by dielectric layers made of SiO
2
, Si
3
N
4
, BPSG or other suitable materials and comprise a plurality of conductive tracks on top of the dielectric layers or in grooves which are formed on the surface of the dielectric layers. These conductive tracks define, in conjunction with contact openings through the dielectric layers, the interconnection structure of the semiconductor device.
To form such an interconnection structure a dielectric layer is deposited on top of the semiconductor substrate or on top of a metallization layer and subsequently anisotropically etched to form contact openings (vias) which extend through the dielectric layer to the metallization layer or to the substrate. In the next step, the vias are filled with an electrical conductive material such as tungsten or polysilicon. Finally, a metal layer is deposited on top of the dielectric layer and subsequently structured.
In another approach to form an interconnection structure grooves are additionally formed in the dielectric layer after the formation of the contact openings. The grooves which are partially in contact with the contact openings define the location of the conductive tracks. Preferably, the grooves and the contact openings are completely filled with a conductive material in one step. The conductive material is subsequently polished back to the top surface of the dielectric layer in order to obtain a plain surface with completely filled grooves. This method is called a dual damascene process.
The materials mainly used for the metallization are aluminum, tungsten and polysilicon. However, as the structuring size of the semiconductor device is scaled down to submicron dimensions, the electrical resistance of the vias and the conductive tracks increases due to the reduced cross-section of the conductive structures. To overcome this problem, the use of highly conductive materials such as copper (Cu) has been proposed. Unfortunately, copper tends to diffuse into the dielectric layer and the active areas of the semiconductor substrate and therefore has to be completely encapsulated by a metal diffusion barrier. An appropriate material for such a diffusion barrier is for instance tantalum (Ta) (see U.S. Pat. Nos. 5,714,418; 5,528,599, and 5,817,572).
Due to adhesion problems of tantalum to a variety of dielectric materials such as SiO
2
, an additional tantalum nitride layer (TaN) between the Ta and the dielectric layer has been suggested (see published European patent application EP 0 751 566 A2). Since TaN can only be deposited by a PVD process it is difficult to obtain a thin and highly conformal layer, which is very important for reliable interconnections of submicron size.
SUMMARY OF THE INVENTION
The present invention describes a microelectronic structure comprising:
a first layer;
a metal nitride layer TiN or WN covering at least partially the first layer;
a tantalum layer on top of the metal nitride layer; and
a metal layer on top of the tantalum layer.
By using titanium nitride (TiN) or tungsten nitride (WN) instead of tantalum nitride as the adhesion layer, it is possible to obtain a very thin and uniform layer. Moreover, TiN and WN act additionally as a diffusion barrier against the diffusion of Cu. Preferably, TiN or WN is deposited by a highly conformal CVD-process.
The invention further provides a microelectronic structure comprising:
a first layer, which covers at least partially a second layer having conductive regions;
the first layer having an upper and a lower surface, the upper surface having grooves formed therein, some of the grooves having openings extending to the lower surface to expose the conductive regions of the second layer;
CVD-deposited metal nitride layer comprises a material selected from the group consisting of TiN and WN, which lines completely the grooves and the openings of the first layer;
a tantalum layer on top of the metal nitride layer; and
a metal layer on top of the tantalum layer, whereat the grooves and openings are substantially filled by the metal layer.
The present invention further provides a method of forming a microelectronic structure having a first layer. The method comprises the following steps:
conformally depositing a metal nitride layer on the first layer, the metal nitride layer comprises a material selected from the group consisting of TiN and WN;
depositing a tantalum layer on top of the metal nitride layer; and
depositing a metal layer on top of the tantalum layer.
In accordance with an added feature of the invention, the metal layer is completely separated from the first layer by the metal nitride layer and the tantalum layer.
In accordance with an additional feature of the invention, the metal nitride layer has a thickness ranging from about 5 nm to about 30 nm.
In accordance with another feature of the invention, the tantalum layer has a thickness ranging from about 10 nm to about 50 nm.
In accordance with again another feature of the invention, the metal layer is formed of Cu, Al, or a Cu-alloy.
In accordance with a further feature of the invention, the first layer has an upper surface with grooves formed therein, the grooves being lined by the metal nitride layer and the tantalum layer, and the grooves being substantially filled by the metal layer.
In accordance with a concomitant feature of the invention, a second layer is formed with conductive regions, the first layer at least partially covering the second layer, the first layer having an upper surface and a lower surface and openings formed therein extending from the upper surface to the lower surface to expose the conductive regions of the second layer, the openings being substantially filled by the metal layer.
Although the invention is illustrated and described herein as embodied in microelectronic structure and method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5221449 (1993-06-01), Colgan et al.
patent: 5268806 (1993-12-01), Goubau et al.
patent: 5281485 (1994-01-01), Colgan et al.
patent: 5744394 (1998-04-01), Iguchi et al.
patent: 5847463 (1998-12-01), Trivedi et al.
patent: 0 751 566 A2 (1997-01-01), None
Japanese Patent Abstract JP 01042857 (Toshio), dated Feb. 15, 1989.
Japanese Patent Abstract JP 04035035 (Tsutomu), dated Feb. 5, 1992.
Hoinkis Mark
Ruf Alexander
Schmidbauer Sven
Schnabel Florian
Weber Stefan
Greenberg Laurence A.
Gurley Lynne A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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