Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-18
2001-01-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000
Reexamination Certificate
active
06177340
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to fabrication methods used for semiconductor devices, and more specifically a process used to integrate logic and memory devices on a single semiconductor chip.
(2) Description of Prior Art
Advanced semiconductor chips, now being manufactured in industry, are composed of logic or memory devices. Logic devices are used to process information or data, while memory devices are used for data storage. These two types of devices can be found in almost all computers, however they are usually found on specific chips, reserved for either logic or memory applications. In systems in which logic and memory devices are packaged separately, data signals between the two may have to pass through several levels of packaging, which can result in undesirable propagation delays. In addition the manufacturing costs for fabricating wafers producing only logic chips, and wafers with only memory chips, are greater than if both logic and memory applications can be incorporated on the same chip. Therefore for performance and cost reasons the semiconductor industry has been motivated to produce a semiconductor chip with both the desired logic and memory requirements.
One difficulty encountered when attempting to integrate logic cells, with memory cells that are comprised of embedded dynamic random access memory, (DRAM), devices, is the ability to open contact holes, to regions of a semiconductor substrate, in thick insulator layers. The DRAM devices, comprised of bit line structures, as well as stacked capacitor structures, both located overlaying the semiconductor substrate, require thick insulator layers, to successfully isolate these components from adjacent conductive features. In addition with the use of sub—0.25 uM groundrules, the contact holes in the thick insulator layers can be designed to dimensions as narrow as 0.3 uM, in diameter, resulting in contact hole aspect ratios of about 7 to 1. This high contact hole aspect ratio is not only difficult to create, via anisotropic reactive ion etching procedures, but also difficult to fill, using conventional chemical vapor deposition, or plasma deposition procedures.
This invention will describe a process for integrating logic devices, and an embedded DRAM array, in which the aspect ratio for a contact hole, is reduced to about one half of the aspect ratio for a contact hole, used in conventional logic—DRAM integrations. This is accomplished using a two stage, contact hole opening, with the first stage forming a C1, first contact hole, in only the lower insulator layers, followed by a tungsten fill, which allows contact to underlying features in the logic and DRAM memory regions to be achieved. The second stage of this procedure features the creation of a C2, second contact hole, in upper insulator layers, directly overlying a tungsten filled, C1 contact holes After filling of the C2 contact holes with tungsten, a tungsten filled, narrow diameter, deep contact hole is established, achieved via a two stage procedure, which each procedure resulting in a contact hole with reduced aspect ratios. The first stage of this procedure, used to create tungsten filled, CI contact holes, also creates a dual shaped opening, allowing a damascene, tungsten bit line structure, to be realized, thus reducing bit line resistance, when compared to counterparts fabricated from metal silicide layers. Related prior art, such as Pittikoun et al, in U.S. Pat. No. 5,691,223, describe a process for forming a capacitor over a bit line structure, for DRAM applications, however tungsten silicide is used in place of tungsten, and more importantly a two stage contact hole opening, and fill, used in this invention to reduce the aspect ratio of the contact hole, is not described in this prior art.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a process for fabricating logic devices and an embedded DRAM array on the same silicon chip, or integrated circuit.
It is another object of this invention to reduce the aspect ratio of narrow diameter contact holes, created in thick insulator layers, via use of a two stage contact hole formation procedure, comprised of a narrow diameter, tungsten filled, lower contact hole, and of a overlying, narrow diameter, tungsten filled, upper contact hole.
It is yet another object to create a damascene type, tungsten bit line structure, in a dual shaped contact hole, for the DRAM array cell.
In accordance with the present invention a fabrication process is described for integrating DRAM and logic devices on the same silicon chip, featuring a two stage contact hole opening procedure, to reduce the aspect ratio for narrow diameter contact holes, in thick insulator layers. A first region of a semiconductor substrate is used for the logic devices, while a second region of the semiconductor substrate is used for the embedded DRAM array. An N well region, used for subsequent p channel, (PFET) devices, and a P well region, used for subsequent N channel, (NFET) devices, are formed in the first region of the semiconductor substrate. Insulator filled, shallow trenches are next formed in the logic, as well as the embedded array region, for purposes of isolation. A first gate insulator layer is formed in the logic region, followed by the creation of polysilicon gate structures. After formation of N type, and P type, lightly doped source/drain regions, silicon nitride spacers on the sides of the polysilicon gate structures, and N type, and P type, heavily doped source/drain regions, in the logic region, a titanium silicide layer is formed on the top surface of all polysilicon gate structures, on the top surface of the N type, heavily doped source/drain region, of the NFET devices, and on the top surface of the P type, heavily doped source/drain region, of the PFET devices. After formation of a second gate insulator layer, in the DRAM region, silicon nitride capped, polycide, (metal silicide—polysilicon), gate structures are formed, followed by the formation of N type, lightly doped source/drain regions, in regions of the semiconductor substrate, not covered by the silicon nitride capped, polycide gate structure, and followed by the formation of silicon nitride spacers, on the sides of the silicon nitride capped, polycide gate structures.
Two self-aligned contact, (SAC), openings are formed in a first insulator layer, exposing two source/drain regions, located between silicon nitride capped, polycide gate structures, in the DRAM region of the semiconductor substrate. Polysilicon plugs are then formed in the SAC openings, each contacting a source/drain region. After deposition of a second insulator layer, a wide opening is formed in a top portion of the second insulator layer. A first narrow diameter, lower contact hole opening is formed in the second and first insulator layers, exposing the top surface of a titanium silicide layer, on a P type source/drain region, in the logic region. A second narrow diameter, lower contact hole opening is created in the second insulator layer, in a portion of the first insulator layer, and in a silicon nitride layer, exposing the metal silicide layer, of a silicon nitride capped, polycide gate structure, in the DRAM region. A third narrow diameter, lower contact hole opening is created in the lower portion the second insulator layer, located within the wide opening, previously created in the top portion of the second insulator layer, creating a dual shaped opening, comprised of an upper, wide diameter, opening, and of a lower, narrow diameter opening, exposing the top surface of a first polysilicon plug. A fourth narrow diameter, lower contact hole opening is created in the second insulator layer, exposing the top surface of a second polysilicon plug. All the lower contact openings are filled with tungsten, with a tungsten bit line structure, created in the dual shaped opening, and contacting the first polysilicon plug.
A narrow diameter opening is created in a third insulator layer, directly overlying, and exposing the tungsten fill
Chiang Wen Chuan
Wang Chen Jong
Yoo Chue-San
Ackerman Stephen B.
Nelms David
Nhu David
Saile George O.
Taiwan Semiconductor Manufacturing Company
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