Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-02-27
2001-03-06
Chan, Eddie P. (Department: 2751)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S105000, C711S131000, C711S150000, C711S154000
Reexamination Certificate
active
06199145
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to the field of memory access in a processing system. More specifically, the present invention pertains to the field of intelligently closing pages in a memory system to enhance overall performance in the processing system.
2. Description of Related Art
Faster memory access typically enhances overall performance of computers and other data processing systems. Memory access improvements may result from, among other things, efficient memory access arbitration, efficient memory access circuitry, or both. With system memories being accessed via multiple ports utilizing different types of memory access commands, advancing memory access stream efficiency requires memory access management beyond that provided by the prior art.
Page mode memory access is one technique used with a conventional row address strobe (RAS) and column address strobe (CAS) accessed memory. In a page mode memory system, a row address is provided on a bus to a memory device and the RAS signal is activated when the row address is available to the memory. An entire row of the memory is internally read according to the row address asserted. Similarly, a column address is provided on the bus and the CAS signal asserted to provide externally a subset of the entire row as selected by the column address. The entire row of memory (i.e., an entire page) may be accessed by altering only the CAS signal.
Access to another page of memory is referred to as a page miss if the new page resides in a device accessed by the same RAS signal. A page miss requires that the current page be closed before the new page may be accessed. Thus, the RAS signal must be deasserted and the RAS lines precharged before the new row address can be driven and the RAS signal asserted. A number of clock cycles are consumed when a memory page miss occurs due to the precharge period necessary to open a new page. Unfortunately, since memory access destinations are not always predictable, memory subsystems regularly encounter unexpected page misses and therefore incur the full delay of the precharge period. Memory throughput may be increased by reducing the number of such unexpected page misses.
One example of a prior art technique which attempts to reduce the impact of page misses is to close pages whenever an idle cycle appears on the bus. Such a technique may be used where an idle cycle indicates a high likelihood that the next memory access will be to a different page than that currently being accessed. By closing pages during such idle cycles, the time delay for the precharge can be at least partially absorbed by the idle cycle.
To facilitate efficient memory page closing, current memory chips are capable of executing commands which automatically close pages upon completion. For example, synchronous dynamic random access memories (SDRAMs) can execute read with auto-precharge and write with auto-precharge commands. Thus, if the system can accurately predict when page changes may occur these commands may be utilized to automatically close pages, thereby achieving more efficient operation than may occur if the page miss is later detected and the precharge executed as a separate command.
One complication to implementing an efficient page closing policy is the use of multiple-bank memory architectures. Multiple-bank memories allow more than one bank to remain open at a time, thereby allowing multiple open pages and generally improving memory access efficiency. Such memories do, however, complicate page closing by adding the option of closing all pages, only an affected page (i.e., one which needs to be closed to access the page indicated by the next memory access command), or some other combination of pages.
Another complication to implementing an efficient page closing policy is the use of multiple-port bus bridges to access memory. Such bridges may receive memory access commands from several sources. For example, a prior art bus bridge may communicate with at least a host bus and a secondary bus such as a peripheral components interconnect (PCI) bus. Since the bus bridge arbitrates memory access between the various ports, memory access sequencing may be further disturbed by this arbitration when stream switching occurs.
With these and other complications to page access prediction, configurable page management circuitry may be desirable to allow tuning for a variety of system arrangements. Furthermore, visibility into the arbitration between multiple command ports could enhance page closing decision making. Prior art page management techniques do not adequately consider the effects of selecting commands from different command ports and/or do not allow sufficient configuration of page closing characteristics.
SUMMARY
A page closing method and apparatus for multi-port host bridges is disclosed. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed after a current memory access command. A number of pages of memory are closed in response to the command selected as the next memory access command. The number is determined at least in part on which command port provides the next memory access command.
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Ajanovic Jasmin
Murdoch Robert N.
Williams Michael W.
Chan Eddie P.
Draeger Jeffrey S.
Intel Corporation
McLean Kimberly
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