Method of forming contact to polysilicon gate for MOS devices

Details Method of forming contact to polysilicon gate for MOS devices Method of forming contact to polysilicon gate for MOS devices

1999-12-13

2001-07-17

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S656000

Reexamination Certificate

active

06261935

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming contacts to a polysilicon gate structure for MOS devices.
(2) Description of the Prior Art
The semiconductor industry continuous to place heavy emphasis on gaining device improvements by stressing reductions device feature dimensions. The reduction in device dimensions in general leads to device performance improvements even though the efforts to continue to reduce device features frequently poses unique technical challenges.
The trend toward continued miniaturization of semiconductor devices has led from the field for Very Large-Scale Integrated (VLSI) devices to the field of Ultra Large-Scale Integrated (ULSI) devices. For ULSI devices the target device feature size is now in the micron and sub-micron range where there is development work taking place relating to deep sub-micron sizes that reach below 0.5 um. The attainment of the sharp reduction in device feature sizes has mainly been accomplished with gradual but significant advances in supporting technologies such as photolithography and improved etching techniques such as Reactive Ion Etching (RIE). These developments have been taking place concurrent with improvements in photo-imaging techniques and advancements in exposure methods and the wavelengths of the exposure sources that now reach into the Deep Ultra Violet range. Special techniques such as the application of special layers of material further improve focusing depth and sharpness of focus in creating images in for instance layers of photoresist that are applied to create interconnect lines, vias, contact openings and the like. These techniques are equally applied in the formation of for instance Complementary Metal Oxide Semiconductor (CMOS) devices.
Further reductions in device dimensions have been made possible by the development of more sensitive photoresist materials as well as the rapid development of anisotropic dry etching procedures. These latter two-developments have allowed for the successful transfer of mask images to underlying layers and the successful etching of these layers with very small dimensions of feature size or feature separation. Further major contributors to the downsizing of semiconductor devices have been the development of Low Pressure Chemical Vapor Deposition (LPCVD) and the development of ion implantation that allows for very fine feature size.
Concurrent with the improvements in the method to fabricate semiconductor devices must come improvements in interconnecting these devices. These methods of interconnecting frequently involve interconnecting overlying layers of metal where openings with sizes down to 0.25 and 0.50 micrometers are used. Vias that have such small dimensions offer their own reliability challenges where the materials that are selected to create the via and the connected metal lines are of great concern. While aluminum has mostly been used for interconnecting metal lines, this material poses problems of electromigration and problems of penetration. Alternate methods and materials for metal line formation together with materials that are used for plug fill are being investigated.
The technique of creating complementary n-channel and p-channel devices has long been known and applied in the semiconductor industry. The salient advantage of these devices is their low power usage due to the fact that two transistors are paired as complementary n-channel and p-channel transistors whereby in either logic state (on/off) of the device, one of the two transistors is off and negligible current is carried through this transistor. The logic elements of Complementary Metal Oxide (CMOS) devices drain significant amounts of current only at the time that these devices switch from one state to another state. Between these transitions the devices draw very little current resulting in low power dissipation for the CMOS device.
Referring now specifically to
FIGS. 1
a
through
1
e
, there is shown a cross section of a typical gate electrode of a CMOS device and its surrounding area. The gate electrode is constructed on the surface of a monocrystalline silicon preferably having a crystal orientation of <
100
>, the background substrate dopant is of first conductivity type and preferably p-type, preferably with boron impurity with a concentration in the range of about 5E15 and 5E17 atoms/cm
3
.
FIG. 1
a
shows a cross section of the gate electrode
14
of a NMOS device on the surface of a silicon substrate
10
. A layer of gate oxide
12
has been created over the surface of substrate
10
, via thermal oxidation at a temperature between about 850 and 950 degrees C. to a thickness of between about 70 and 850 Angstrom. A layer
14
of polysilicon is deposited using LPCVD at a temperature between about 550 and 700 degrees C., to a thickness between about 2000 and 4000 Angstrom. The layer
14
of polysilicon is provided with the required conductivity by an ion implant procedure, using phosphorous as a source at an energy between about 50 and 100 KeV with a does between about 1E13 and 5E15 atoms/cm
2
. Standard methods of patterning and RIE etching are applied using SF
6
as an etchant to form the gate electrode
14
.
P-type implant
16
forms deep doped regions
17
(the source region) and
18
(the drain region) in the surface of the substrate
10
, these regions are (due to the masking effect of the poly layer
14
) self-aligned with the gate electrode
14
. Dopant concentrations in regions
17
and
18
are higher than the dopant concentrations in the surrounding substrate
10
.
FIG. 1
b
shows the lightly doped (LDD) regions
20
and
21
are formed by performing for instance an N-type implant
22
into substrate
10
. This N-type implant has a shallower junction depth and a higher dopant concentration than the previously implanted regions
17
and
18
(
FIG. 1
a
). As examples of LDD implants can be mentioned an NMOS implant using arsenic with an energy within the range of between 1 to 10 keV and a dose within the range of between 1e14 to 1e16 atoms/cm
2
. Further can be mentioned an PMOS implant using BF
2
with an energy within the range of between 1 to 10 keV and a dose within the range of between 1e14 to 5e15 atoms/cm
2
.
FIG. 1
c
shows the formation of gate spacers
26
on the sides of the gate electrode
14
. This is performed using another LPCVD process, using tetraethylorthosilicate as a source, to deposit a silicon layer
26
at a temperature between about 500 and 700 degrees C. to a thickness between about 2000 and 4000 Angstrom. Anisotropic selective RIE processing using CH
4
and H
2
as etchants is used to create the silicon oxide sidewall spacers
26
. By performing implant
28
the heavily doped regions
24
and
25
are created in the substrate
10
. Silicide layers are created over the surface of the source/drain regions
24
and
25
(not shown) and on the top surface
30
of the gate electrode
14
. These silicide layers are, as previously indicated, used to interconnect the gate electrode and to connect the gate electrode to surrounding circuitry.
Silicides are often used to reduce contact resistance. For very small modern silicon devices, which are sub-micron, sub-half-micron, and even sub-quarter-micron, conventional photolithographic technique for patterning contacts will not meet the required tolerance of critical dimensions. The method of self-aligned silicide (salicide) formation, which self-registers with the contacts at the top of the polysilicon gate, the source and the drain, helps solve the problem of critical dimension tolerance. Salicides have thus become almost universal in today's high-density MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistors) devices even though the gate metal is now prevalently replaced by the polysilicon gate. Metal silicide can be tungsten silicide deposited using LPCVD, at a temp. between 400 and 600 degrees C. to a thickness between 1000 and 2000 Angstrom and can be titanium silicide f

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