Method of making a multi-level interconnect having a...

Details Method of making a multi-level interconnect having a... Method of making a multi-level interconnect having a...

1998-09-24

2001-03-20

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S625000, C438S648000, C438S653000, C438S656000, C438S685000, C438S927000, C257S751000

Reexamination Certificate

active

06204167

ABSTRACT:

BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device having multi-level wirings and a method of manufacturing the same, and more particularly to a technique of forming multi-layer wirings using refractory metal as a lower level wiring.
b) Description of the Related Art
In a conventional semiconductor device, Al or Al alloy has been mainly used as a stack or layered wiring. Used as a laminate wiring are, for example, an Al/TiN/Ti stack structure having an Al layer and an TiN layer on a Ti layer in this order from the top and an Al/TiN stack structure having an Al layer on the TiN layer. An Al/TiN/Ti stack structure has been generally used particularly for a lower level wiring. In this specification, A/B means that an A layer is stacked upon a B layer.
As semiconductor devices are miniaturized more and more, a wiring width, a contact hole diameter, and the like have become smaller particularly at a lower level wiring. As the pattern size becomes fine, a density of current flowing through an Al wiring increases and electromigration in the Al wiring is likely to cause a resistance increase and a wiring open failure. There is therefore some fear of lowered reliability of semiconductor devices.
Degraded performance such as low endurance or resistance to stress migration caused by fine patterns have also increased reliability concerns.
In order to solve the above problems, attention has been paid to a technique of using refractory metal tungsten (W) instead of Al as a lower level wiring.
FIG. 8
is a cross sectional view of a substrate with a multi-level wiring structure having a similar structure to a conventional Al multi-level wiring structure and using an W layer as a lower level wiring. On a silicon substrate
50
, a boro-phospho-silicate glass (BPSG) film
51
is formed. A Ti film
52
, a TiN film
53
, and a W film
54
are deposited on a predetermined surface area of the BPSG film
51
in this order from the bottom to form a lower level wiring. The lower level wiring is electrically connected to a silicon substrate
50
or a polycrystalline silicon electrode at a contact region (not shown) through a contact hole formed in the BPSG film
51
.
An inter-level insulating film
55
is formed on the lower level wiring and the BPSG film
51
. A connection or via hole is formed in the inter-level insulating film
55
for electrical connection to the lower level wiring. An upper level wiring of a stack or laminate structure having a Ti layer
56
and an Al alloy layer
57
thereon is formed on the inter-level insulating film
55
. The upper level wiring is electrically connected to the lower level wiring through the connection hole formed in the inter-level insulating layer
55
.
With the multi-level wiring structure shown in
FIG. 8
, contact resistance between the Al alloy layer
57
and W layer
54
increases because of heating during the formation of a passivation film after forming the upper level wiring or because of heating during annealing.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a multi-level wiring forming technique capable of suppressing an increase of contact resistance between an upper level wiring and a lower level wiring even if refractory metal is used as the lower level wiring and a heat treatment is performed after the upper level wiring is formed.
According to one aspect of the present invention, there is provided a semiconductor device comprising: an underlie having a first insulating layer; a first wiring containing refractory metal as a main composition thereof and formed on said first insulating layer; a second insulating layer formed on said first wiring and having a contact hole on a desired region of the first wiring; a second wiring containing Al as a main composition thereof and formed on said second insulating layer to be electrically connected to an upper surface of said first wiring at a region of said contact hole; and a barrier layer formed between said first and second wirings at a portion where said first and second wirings are electrically connected, said barrier layer being made of a material different from, and substantially not reacting with, both Al and the refractory metal.
The term “main composition” means a composition of 90% or more, and typically a composition of 98% or more. The term “not substantially reacting” means a degree of reactivity giving no significant change in contact resistance between the first and second wirings. If reaction occurs between a barrier layer and an upper or lower level wiring layer, the contact resistance therebetween usually increases two or three times as large as that immediately after forming the wirings, at the completion of all the processes.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a first wiring on a substrate having a first insulating layer on a surface thereof, said first wiring containing refractory metal as a main composition thereof; forming a second insulating layer on said first wiring; forming a via hole in said second insulating layer so as to expose a surface of said first wiring; forming a barrier layer at least on the exposed surface of said first wiring at a bottom of said via hole, said barrier layer being made of a material different from, and not substantially reacting with, both Al and, the refractory metal; slightly oxidizing a surface of said barrier layer to form an oxidized surface layer; and forming a second wiring layer on said second insulating film and said oxidized surface layer, said second wiring layer containing Al as a main composition thereof.
An increase of contact resistance between the first wiring of refractory metal and the second wiring of Al or Al alloy may be ascribed to reaction between refractory metal and Al. A barrier layer is formed at an interface between the first wiring or refractory metal and the second wiring of Al or Al alloy to be formed on the first wiring, the barrier layer being made of a material not substantially reacting with both the refractory metal and Al or Al alloy. In this manner, an increase of contact resistance between the first and second wirings, which would otherwise be caused by reaction between the first and second wiring materials, can be prevented. The barrier layer may scarcely or slightly react with the first and second wirings, provided that the adverse effects by byproduct can be neglected and a non-reacted barrier layer is left.
Prior to forming an Al alloy layer of the second wiring layer on the barrier layer, a thin oxidized surface layer is formed on the barrier layer. If an Al alloy layer of the second wiring layer is directly formed on the barrier layer, resistance to electromigration in the second wiring layer is lowered. However, by forming a thin oxidized surface layer on the barrier layer, it is possible to prevent resistance to electromigration from being lowered.
As above, an increase of contact resistance between a first wiring layer of refractory metal and a second wiring layer formed on the first wiring layer can be suppressed and the reliability and performance of semiconductor devices can be improved.


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