Method of manufacturing transistor barrier layer

Details Method of manufacturing transistor barrier layer Method of manufacturing transistor barrier layer

1998-03-17

2001-08-21

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S629000, C438S642000, C438S648000, C438S655000, C438S656000, C438S672000, C438S675000

Reexamination Certificate

active

06277729

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No.86118305, filed Dec. 5, 1997, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a transistor manufacturing process. More particularly, the present invention relates to a method for manufacturing a transistor barrier layer.
2. Description of Related Art
In the metallization of integrated circuits, low resistivity material such as aluminum or tungsten is quite often used in forming the conductive wires for forming links between devices. However, due to the formation of spikes at the contact interface between aluminum and silicon, contact resistance becomes very high. Hence, when either aluminum or tungsten is used to form metallic wiring, a conductive barrier layer is often formed at the contact interface. This not only will prevent the formation of spikes, but also can increase the adhesion of tungsten layer to other material. Commonly used material for forming barrier layer includes titanium nitride and tungsten nitride, but titanium nitride is more frequently used.
To increase the strength of ohmic contact of metal with silicon, the barrier layer is usually formed as a titanium/titanium nitride composite layer. Titanium is a kind of metal having a good oxygen gettering capability. At a temperature of about 500° C., titanium and silicon atoms at the metal/silicon interface will cross-diffuse to form a titanium silicide layer having a rather low resistivity, thereby forming a good ohmic contact. The method of forming a titanium silicide layer for lowering the resistance and ensuring a good shallow junction between MOS transistor terminal and the metallic connection is known as a self-aligned silicide (Salicide) process.
FIGS. 1
a
through
1
f
are cross-sectional views showing the progression of manufacturing steps in the conventional process of forming a barrier layer. First, as shown in
FIG. 1
a
, a semiconductor substrate
100
is provided. The semiconductor substrate
100
has a field oxide layer on each side and a patterned gate terminal
106
. In addition, silicon oxide spacers
104
are formed on the sides of the gate terminal
106
.
Next, as shown in
FIG. 1
b
, titanium is deposited over the whole wafer using a DC sputtering method, thereby forming a titanium layer
108
above the transistor.
Next, as shown in
FIG. 1
c
, using a high temperature, the titanium film
108
is allow to react with the silicon above the drain and source terminals as well as the polysilicon above the gate terminal of a MOS transistor to form titanium silicide layers
105
. This is a self-aligned silicide process, and through this process, the contact resistance is lowered and a good shallow junction between the terminal of a MOS transistor and a metallic layer can be obtained.
Next, as shown in
FIG. 1
d
, a wet etching method is used to remove the unreacted titanium layer
108
and exposing the titanium silicide layers
105
above the three terminals of the MOS transistor.
Next, as shown in
FIG. 1
e
, a dielectric layer
110
deposited over the wafer surface using a chemical vapor deposition method. Then, a pattern is formed on the dielectric layer
110
and then etched to form via channels exposing a portion of the titanium silicide layer
105
.
Next, as shown in
FIG. 1
f
, a titanium layer
112
having a desired thickness is deposited over the wafer using a sputtering method, and then a nitridation reaction is carried out to form a titanium nitride layer
114
. A nitridation reaction is performed by placing the wafer into a nitrogen-filled or ammonia-filled reaction chamber, and then using rapid thermal processing for nitriding the titanium layer into a titanium nitride layer. Thereafter, a tungsten layer is deposited into the via and surrounding areas followed by a planarizing operation of the tungsten layer. Finally, a tungsten plug
116
is formed. Nevertheless, without rapid thermal processing, the titanium/titanium nitride composite layer has a rather high contact resistance. Hence, a rapid thermal processing operation is added for lowering the contact resistance. However, the rapid thermal processing operation often will lead to the formation of cracks in the titanium nitride layer, and stringers may form when the tungsten is etched back to form the tungsten plug
116
. These stringers may lead to the short-circuiting of the transistor and an increase the contact resistance. If a collimator sputtering method is used to form the titanium/titanium nitride composite layer, the formation of cracks in the titanium nitride layer may even be more severe.
On the other hand, if a titanium layer is deposited first followed by a rapid thermal processing operation to form the titanium nitride layer, the titanium nitride reaction will tend to compete with the titanium silicide reaction. Consequently, less titanium silicide will be formed and hence the contact resistance will increase. Besides, compounds of titanium-nitrogen-oxygen formed at the upper layer will also affect the contact resistance.
Therefore, in the past, titanium/titanium nitride thin film is often used as a barrier layer and a glue layer for contact window in the metallization of integrated circuits. The use of rapid thermal processing after the deposition of the titanium/titanium nitride thin film is capable of lower contact resistance with metal. However, the titanium nitride layer will generate cracks that will result in stringers in the tungsten plug, and leading to short-circuiting of the transistor. The situation will be more serious when collimator-sputtering method is used to form the titanium nitride layer. If a rapid thermal processing operation is performed right after the deposition of titanium layer, and then the titanium nitride layer is subsequently deposited to form the barrier layer, cracks formation in the titanium nitride layer can be greatly reduced. This, however, will lead to a high contact resistance, and is especially serious when a self-aligned silicide process is used on a titanium layer.
In light of the foregoing, there is a need to provide an improved method of forming a barrier layer over MOS transistor terminals.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a process for manufacturing a barrier layer that can avoid the appearance of cracks in the titanium nitride layer, thereby preventing the formation of stringers in tungsten plug that may lead to a short-circuiting of transistor.
In another aspect, the invention provides a process for manufacturing a barrier layer that has a lower contact resistance.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for manufacturing a barrier layer over the transistor terminals. The method includes an ion bombardment treatment after the deposition of a titanium nitride layer in order to decrease contact resistance as well as to avoid the production of stringers in the tungsten plugs. The method comprises the steps of providing a substrate having a patterned transistor already formed thereon, and then forming a metallic layer and a metallic nitride layer over the transistor. Next, an ion bombardment treatment is performed, and then a rapid thermal processing operation is carried out in a nitride ions filled gaseous atmosphere. Finally, a tungsten layer is deposited over the metallic nitride layer, and then the tungsten layer is patterned and planarized. Thereafter, subsequent processing operations for completing the device are performed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5397744 (1995-03-01), Sumi et al.
patent: 5565708 (1996-10-01), Ohsaki et al.
patent: 5619057 (1997-04-01), Komatsu
patent: 5723362 (1998-03-01), Inoue et al.

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