Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-01
2001-04-03
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S655000, C438S683000
Reexamination Certificate
active
06211054
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of forming conductive lines, and more specifically to methods of forming local interconnects.
BACKGROUND OF THE INVENTION
The reduction in memory cell and other circuit size in high density dynamic random access memories (DRAMs) and other circuitry is a continuing goal in semiconductor fabrication. Implementing electric circuits involves connecting isolated devices through specific electric paths. When fabricating silicon and other semiconductive materials into integrated circuits, conductive devices built into semiconductive substrates typically need to be isolated from one another. Such isolation typically occurs in the form of either trench and refill field isolation regions or LOCOS grown field oxide.
Conductive lines, for example transistor gate lines, are formed over bulk semiconductor substrates. Some lines run globally over large areas of the semiconductor substrate. Others are much shorter and associated with very small portions of the integrated circuitry. This invention was principally motivated in making processing improvements in the fabrication of local interconnects, although the invention is not so limited. As device dimensions continue to shrink, so do the size of local interconnects.
SUMMARY
The invention includes methods of forming conductive lines, such as local interconnects. In one implementation, a method of forming a conductive line includes depositing a first layer comprising polymer silicon on a substrate. A metal is deposited at least over some portion of the first layer and a metal silicide is formed from reaction of the metal with silicon of the polymer silicon over the at least some portion. The metal silicide is provided into a desired conductive line shape.
In one implementation, a method of forming a conductive line includes depositing a first layer comprising polymer silicon or amorphous silicon on a substrate. Only a portion of the first layer is exposed to both oxygen and ultraviolet light effective to transform at least an outer part of the portion to oxidized silicon. After the exposing to both oxygen and ultraviolet light, a metal layer is deposited at least over some portion of the first layer which was not subjected to the effective exposing to the combination of oxygen and ultraviolet light. After depositing the metal layer, the substrate is exposed to annealing conditions effective to form a metal silicide over the at least some portion. After the annealing, metal is removed from the metal layer which has not been transformed to metal silicide substantially selective relative to metal which has been so transformed.
REFERENCES:
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patent: 6025117 (2000-02-01), Nakano et al.
patent: 2543581 (1984-10-01), None
Monget, C., et al., “Application of Plasma Polymerized MethylSilane for 0.18 &mgr;m Photolithography”, 10 pages (undated).
Hu Yongjun Jeff
Li Li
Anya Igwe U.
Micro)n Technology, Inc.
Smith Matthew
Wells, St. John, Roberts Gregory & Matkin P.S.
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