Abrading – Abrading process – With tool treating or forming
Reexamination Certificate
1999-11-24
2001-08-28
Banks, Derris H. (Department: 3723)
Abrading
Abrading process
With tool treating or forming
C451S444000
Reexamination Certificate
active
06280298
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and methods for the cleaning of test probes. In particular, the present invention relates to oxidizing debris on a test probe with an oxidizing agent and removing the oxidized debris with a cleaning agent.
2. State of the Art
In a typical semiconductor device manufacturing process, a plurality of integrated circuitry (IC) components are formed on a wafer, such as a silicon wafer. Once the IC components are formed, the wafer is diced into individual chips. These chips are then packaged for use, as known in the art.
The formation of the IC components requires numerous individual processing operations, primarily material layering and patterning, performed in a specific sequence. Each of these operations must be precisely controlled and monitored so that the IC components operate with the required electrical characteristics. However, even though the operations are precisely controlled and monitored, IC component failures still occur. Thus, it is important to detect the defective IC components as early as possible to prevent the unnecessary expense of continuing the fabrication of the defective IC components.
The IC components are generally tested after they are fabricated on the wafer and just prior to the dicing the wafer into individual chips. A typical method of testing the electrical characteristics of the IC components requires physical contact with the wafer surface. As shown in
FIG. 7
, the physical contact generally comprises contacting a plurality of bond pads
202
on an IC wafer
204
(defined as a wafer having IC components and material layers thereon) with a plurality of test probes
206
housed in a probe housing
208
. The test probes
206
are usually fabricated from metal material and reside in vias
212
that extend into the probe housing
208
. The test probes may be biased by a spring mechanism
214
. The test probes
206
are each in electrical contact with traces
216
(shown as dashed lines) within the probe housing
208
which directs electrical test signals to the IC wafer
204
. The test probes
206
extend out of the probe housing vias
212
to contact the IC wafer bond pads
202
. The IC wafer bond pads
202
are in electrical contact with IC components (not shown) through a plurality of traces
218
(shown as dashed lines) within the IC wafer
204
.
As shown in
FIG. 8
, each test probe
206
has a tapered tip
222
that presses into the IC wafer bond pad
202
. Pressing the test probe tapered tip
222
into the IC wafer bond pad
202
helps ensure that the test probe
206
makes sufficient electrical contact with the IC wafer bond pad
202
for testing purposes. Thus, the IC component within the IC wafer
204
can be tested for specific electrical characteristics by sending and/or receiving signals through the test probe
206
. The IC components that fail the test procedure are “mapped” such that when the IC wafer
204
is diced the chips containing the failing IC components can be culled.
The IC wafer bond pad
202
is general made from a conductive material, including copper, aluminum, solder (lead/tin alloy), or the like. One problem which occurs in such a testing procedure is the buildup of debris
224
on the test probe tapered tip
222
, as shown in FIG.
9
. The debris
224
primarily comprises the conductive material of the IC wafer bond pad
202
that is “picked” off the IC wafer bond pad
202
by the test probe tapered tip
222
, and/or otherwise coats the test probe tapered tip
222
. The debris
224
can prevent sufficient electrical connectivity between the test probe
206
and the IC wafer bond pad
202
. If sufficient electrical connectivity is not achieved, the test procedure will result in a false fail indication, which may result in a potential culling of a “good” IC chip. Thus, the debris
224
must be removed from the test probe tapered tips
222
.
One method of cleaning test probes
206
is to manually brush or otherwise abrade the test probe tapered tips
222
. However, an abrasive method can spread the debris
224
and can wear the critical tapered tips
222
of the test probes
206
.
A non-abrasive method of cleaning test probe tapered tips
222
is to spray a chemical solvent on the test probes
206
to dissolve the debris
224
. However, such cleaning processes can force the debris
224
and moisture into the probe housing
208
. The debris
224
and moisture can cause ionization, which can result in leakage and shorting failures, thus yielding erroneous test results. Furthermore, the debris
224
can become trapped in the probe housing vias
212
that can cause the test probe
206
to stick in the probe housing via
212
and not contact the IC wafer bond pad
202
. Thus, the stuck test probe would generate a false fail indication.
Therefore, it would be advantageous to develop apparatus and techniques to clean test probes while eliminating the inherent problems with present techniques of test probe cleaning.
SUMMARY OF THE INVENTION
The present invention relates to apparatus and methods for cleaning debris from a test probe. Debris is cleaned from the test probe by oxidizing the test probe debris in an oxidizing agent and dissolving said oxidized debris in a cleaning agent.
REFERENCES:
patent: 4314855 (1982-02-01), Chang et al.
patent: 5728229 (1998-03-01), Despres
Banks Derris H.
Intel Corporation
Winkle Robert G.
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