Resurf LDMOS device with deep drain region

Details Resurf LDMOS device with deep drain region Resurf LDMOS device with deep drain region

1999-05-27

2001-04-03

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S336000, C257S338000, C257S408000

Reexamination Certificate

active

06211552

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor devices and, more particularly, to a RESURF (REduced SURf ace Field) LDMOS (lateral double-diffused “metal” N-oxide-semiconductor) device having a deep buffer implant in the drain region and method of fabrication thereof.
BACKGROUND OF THE INVENTION
LDMOS devices are the devices of choice in the 20-60V range. LDMOS devices are very easy to integrate into a CMOS or BiCMOS process thereby facilitating the fabrication of control, logic, and power switches on a single chip. In the 20-60V range, optimized LDMOS devices are also much more efficient in terms of on-state voltage and switching losses than power bipolar junction transistors or other hybrid MOSbipolar devices.
Optimized LDMOS design seeks to provide power switches with very low specific on-state resistance (Rsp) while maintaining high switching speed. A low Rsp helps reduce power losses as well as the size of the die. RESURF LDMOS or RLDMOS devices are very attractive in this respect as they offer very good trade-off between Rsp and breakdown voltage (BV) capability compared to non-RLDMOS devices. RLDMOS devices use the Reduced Surface electric field phenomenon to increase the drift region doping for a given breakdown voltage. The increased drift region doping causes reduction in the drift region resistance leading to an overall lower Rsp for the device.
As device size shrinks, the desire to maintain as wide a Safe Operating Area (SOA) as possible remains, since the applications these devices are used in remain the same. However, shrinking RESURF LDMOS device size has a negative impact on the robustness of the device. Accordingly, a need exists for a RESURF LDMOS device having improved robustness.
SUMMARY OF THE INVENTION
Applicants have discovered that factors contributing to the failure of conventional RLDMOS devices during reverse breakdown include the presence of a high electric field at the location where the RESURF region overlaps the n+drain region and a correspondingly high impact ionization rate near the drain region and low snap back current.
Generally, and in one form of the invention, a transistor includes:
a semiconductor layer of a first conductivity type;
a RESURF region of a second conductivity type formed in the semiconductor layer;
a LOCOS field oxide region formed at a face of the RESURF region, the RESURF region being self-aligned to the LOCOS field oxide region;
a well of the first conductivity type formed in the semiconductor layer;
a source region of the second conductivity type formed in the well, a channel region defined in the well between a first edge of the source region and a first edge of the RESURF region;
a drain region of the second conductivity type formed in the semiconductor layer adjacent a second edge of the RESURF region, the drain region including a first region extending from the face of the semiconductor layer to a first distance below the face of the semiconductor layer and a second region surrounding the first region and extending a second distance below the face of the semiconductor layer, the first distance being less than the second distance and the first region being more heavily doped than the second region; and
a conductive gate formed over and insulated from the channel region.


REFERENCES:
patent: 5304827 (1994-04-01), Malhi et al.
patent: 5627394 (1997-05-01), Chang et al.

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