Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1997-08-18
2001-07-03
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S050510, C174S260000, C257S778000
Reexamination Certificate
active
06255599
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to packaging semiconductor devices. More specifically, this invention relates to packaging semiconductor devices with laminar substrates using the flip chip packaging technique.
2. Description of the Related Art
The drive to higher semiconductor device densities requires that the packaging of a device or chip support these new densities. One technique that supports the increased device densities is the shift from peripheral wire bonding to area array chip interconnects. Area array chip interconnects use bumps or solder joints that directly couples the semiconductor chip to the package substrate. This technique accommodates the increased I/O pad counts and brings current to the interior of the chip, which improves the voltage noise margins. One type of area array interconnect packaging technique is the flip chip (FC) solder interconnect on a substrate. In the flip chip assembly or package, the semiconductor device or integrated circuit (IC) chip typically has bumps for soldering (FC solder joints) manufactured on the I/O pads of the chip (the top or etched side of the IC chip), which takes the place of the wire bonding pads. The chip is then turned upside down or “flipped” so that the device side or face of the IC chip couples to a substrate such as found in a plastic ball-grid-array (PBGA) substrate (or laminate).
One problem associated with the flip chip packaging technique occurs because of the large differences or mismatch between the coefficient of thermal expansion (CTE) of silicon (the IC chip) and the CTE of the PBGA substrate. The CTE of silicon is about 3 ppm per degree Centigrade and that of the PBGA substrate is about 17 ppm per degree Centigrade. The large difference in CTE causes the solder joints between the IC chip and the PBGA substrate to undergo shear stress during temperature changes, which can occur during the regular manufacturing process or even during the daily use of the package when used in a product. This repetitive heating up and cooling down of the package can cause reliability problems in a flip chip package that may cause it to fail prematurely and or suffer degraded performance.
One technique used to transfer some of the shear stress away from the FC solder joints is to use an encapsulant as an underfill material between the device side of the IC chip and the top surface of the PBGA substrate. After the encapsulant cures, the bonding of the encapsulant shifts most of the shear stress away from the solder joints and redistributes the stress across the IC chip, the substrate, and the encapsulant as a whole (also known as the package, the assembly, or the encapsulated flip chip package). Although the use of an encapsulant reduces some problems, its use creates new problems. One problem created when using an encapsulant is warpage. Warpage occurs because of the mismatches of the CTE of the IC chip and the CTE of the PBGA laminate. When the encapsulant cures, the substrate and the chip are initially flat. After the encapsulated FC PBGA cools down (to room temperature), the substrate will shrink more than the IC chip and cause the back side of the IC chip to be higher in the center (bulge up) and lower at the corners. This warpage in the assembled flip chip package causes compression stresses on the device side of the IC chip and tensile stresses on the back side of the IC chip. An excessive tensile stress may cause the IC chip to crack, and an excessive stress on the flip chip package may cause interfacial delamination between the IC chip and the encapsulant and or between the encapsulant and the substrate.
The present invention is a collection of techniques that overcome the above disadvantages and improve the overall reliability of the flip chip packaging technique. One may practice the different techniques of the present invention separately or in combination with one another. The present invention will reduce the probability of an IC chip crack due to excessive stresses (this also includes reducing the probability of stress enhanced electromigration of the metal lines on an IC chip) that includes warpage. Additionally, the present invention will reduce the probability of an interfacial delamination between the IC chip and the encapsulant and or between the encapsulant and the substrate. And, the present invention will also improve the reliability of the flip chip packaging technique in its daily use under repetitive thermal cycles of normal use when used as part of a product.
The present invention discloses one embodiment that relocates the neutral plane in a PBGA laminate. This embodiment of the present invention reduces the compression stress on the device side of the IC chip and reduces the tensile stress on the back side of the IC chip that occurs when the encapsulated flip chip package cools from its wiring board assembly temperature to room temperature.
Another embodiment of the present invention controls the stiffness of individual layers within the PBGA laminate with a gradual reduction of stiffness from the bottom side to the top side of the laminate. This embodiment reduces warpage and the shear stress on the IC chip solder joints.
Another embodiment of the present invention uses redundant solder joint connections between the encapsulated flip chip package and the printed wiring board. These additional solder joint connections help reduce the bending of the IC chip and help improve the placement of any heat sink on the back side of the IC chip. Reducing the bending of the IC chip also helps improve its thermal performance with a heatsink. The thermal performance is especially important when using high power IC chips that require a high capacity heat sink.
SUMMARY OF THE INVENTION
The present invention discloses a collection of techniques that improve the reliability of a flip chip (FC) plastic ball grid array (PBGA) assembly. One may practice the different techniques of the present invention separately or in combination with one another. The present invention reduces cracking of the IC chip due to excessive stresses such as warpage. Additionally, the present invention reduces the interfacial delamination between the IC chip and the encapsulant and or between the encapsulant and the substrate. And, the present invention improves the reliability of the flip chip packaging technique under repetitive thermal cycles of normal use.
One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the PBGA substrate away from its mid-plane. One technique to relocate the neutral plane is to relocate the neutral plane during the fabrication of the structure.
Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in flip chip packaging that arranges the layers of the laminate according to the stiffness of each layer. The present invention arranges the layers in the laminate from the top to the bottom of the laminate where the least stiff layer is at the top of the laminate and the most stiff layer is at the bottom of the laminate. One technique to vary the stiffness of the metal layers is to vary the diameter of the via holes that go through the metal layer.
Another embodiment of the present invention describes a method and apparatus of packaging a flip chip assembly that uses one or more redundant interconnections between the PBGA substrate and the printed wiring board. The redundant interconnections are at the bottom of the package substrate and are within the shadow of the IC chip. The present invention routes all signal paths and some of the power and ground connections to areas on the bottom of the package substrate that are outside the shadow of the IC chip with non-critical redundant power and ground connections routed to the area within the shadow of the IC chip.
REFERENCES:
patent: 4888061 (1989-12-01), Wenz
patent: 5463191 (1995-10-01), Bell et al.
patent: 5627407 (1997-05-01), Suhir et al.
patent: 5796590 (1998-08-01),
Chang Chi Shih
Chen William T.
Trivedi Ajit
Blakely & Sokoloff, Taylor & Zafman
IBM
Paladini Albert W.
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