Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-06-12
2001-03-27
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S063000
Reexamination Certificate
active
06208572
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates generally to semiconductor memory devices, and more specifically, to test circuitry for semiconductor memory devices.
2. Related Art
A typical semiconductor static random-access memory (SRAM) device includes word lines, a pair of bit lines, and memory cells with cell latches and pass devices connected at intersections between the word lines and the pair of bit lines. The pass devices of the memory cells are connected to the pair of bit lines through bitline contacts. During a read or write operation, these bitline contacts allow the contents of the memory cell to be successfully read from or written into the cell latch. Bitline contacts that have too much resistance (resistive bitline contacts) will not properly allow the memory cell to be read from or written into. Resistive bitline contacts may occur as a result of mechanical failures or non-conductive materials that are formed between the pass devices and the bitline, and are hard to detect since the pass devices have a large series resistance (e.g., typically in the 10K ohm range) compared to the resistive bitline contact.
Although bitline contacts may be tested with the testing of the memory cell or bitlines, most manufacturing tests have difficulty recognizing a borderline resistive bitline contact and will generally pass the bitline contact and memory cell. When the resistive bitline contact is then used in the system under a slightly different voltage and/or temperature, the resistive bitline contact may then fail, rendering the corresponding memory cell inoperable.
Accordingly, a need has developed in the art for a semiconductor memory device test that will improve detection of resistive bitline contacts.
SUMMARY OF THE INVENTION
The present invention provides a memory device having resistive bitline contact testing, wherein two cells are activated simultaneously to allow higher current through the bitline contact for improved detection of resistive bitline contacts. A test cell may also be included to test the integrity of the bitline contact.
Generally, the present invention provides a memory device comprising:
a first and second memory cell;
a bitline for providing data to said first and second memory cell;
a bitline contact coupling said bitline to said first and second memory cell;
a first and second wordline signal for activating said first and second memory cell, respectively, to receive said data from said bitline; and
a wordline logic device, receiving said first and second wordline signal and transmitting said first and second wordline signal to said first and second memory cell, respectively,
wherein during a test of said bitline contact, said wordline logic device transmits said first and second wordline signal to said first and second memory cell essentially simultaneously.
In addition, the present invention provides a method for testing the resistance of a bitline contact in a memory device having memory cells comprising the steps of:
a) writing a data value into adjacent memory cells sharing said bitline contact;
b) reading said data value from said adjacent memory cells essentially simultaneously; and
c) comparing said read data value of said adjacent memory cells with said written data value.
The present invention also provides an SRAM memory array system comprising:
a plurality of adjacent memory cells;
a bitline for transferring data values to or from said plurality of adjacent memory cells;
a plurality of bitline contacts coupling said bitline to said plurality of adjacent memory cells, each of said plurality of bitline contacts being shared between each of said plurality of adjacent memory cells, respectively;
a plurality of wordline signals for activating said plurality of adjacent memory cells, for transferring said data values to said bitline; and
a plurality of wordline logic devices, receiving said plurality of wordline signals, each of said plurality of wordline logic devices receiving two of said plurality of wordline signals, and transmitting said plurality of wordline signals to said plurality of adjacent memory cells,
wherein during a test of each of said plurality of bitline contacts, each of said plurality of wordline logic devices transmits said two of said plurality of wordline signals to each of said plurality of adjacent memory cells essentially simultaneously.
The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention, as illustrated in the accompanying drawings.
REFERENCES:
patent: 5250854 (1993-10-01), Lien
patent: 5291433 (1994-03-01), Itoh
patent: 5463580 (1995-10-01), Nakamura
patent: 5491665 (1996-02-01), Sachdev
patent: 5550771 (1996-08-01), Hatori
patent: 5872018 (1999-02-01), Lee
Adams R. Dean
Busch Robert E.
Pilo Harold
Rudgers George E.
Capella Steven
International Business Machines - Corporation
Mai Son
Schmeiser Olsen & Watts
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