Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-05-12
2001-07-24
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06266798
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi power supply integrated circuit evaluating system for evaluating a multi power supply integrated circuit employing a plurality of power supply voltages and a method of operating the same and, more particularly, a multi power supply integrated circuit evaluating system for evaluating the connectivity between constituent elements of a multi power supply integrated circuit and a method of operating the same.
2. Description of the Related Art
With the increase of the integration density of the semiconductor integrated circuit, lower power consumption is requested more and more. Most of the power consumption of the CMOS circuit constituting the semiconductor integrated circuit is caused by charge and discharge of the load capacitance. For example, there are a drain capacitance, a gate capacitance, etc. of the MOS transistor constituting the CMOS circuit as the load capacitance. It is very effective for the lower power consumption of the CMOS circuit to reduce the power supply voltage. However, if the power supply voltages of allover circuit are reduced uniformly, a circuit operation becomes slow. As a result, a breach of the constraint in the circuit timing is brought about, so that there is a possibility that the circuit does not operate normally. For this reason, there has been proposed the approach in which a high potential cell (VDDH cell) driven by a high potential power supply voltage (VDDH) is employed in critical paths with a high timing accuracy and also a low potential cell (VDDL cell) driven by a low potential power supply voltage (VDDL) is applied to paths with a margin in the timing accuracy. According to this approach, lower power consumption of the CMOS circuit can be achieved while maintaining a high speed performance of overall circuit.
According to such design concept, the inventors of the present invention have examined the multi power supply integrated circuit. As a result, it has been found that, in the CMOS circuit utilizing multi power supply voltages, for example, two power supply voltages consisting of a high potential power supply voltage (VDDH) and a low potential power supply voltage (VDDL), a through current is generated in the high potential cell being driven by a high potential power supply voltage if a particular connectivity can be achieved, as described in the following.
FIG. 1
is an equivalent circuit diagram showing a part of a dual power supply integrated circuit employing two power supply voltages. As shown in
FIG. 1
, the dual power supply integrated circuit is composed of a CMOS circuit which constitutes a high potential cell (VDDH cell)
101
which is driven by a high potential power supply voltage (VDDH) and consists of a p-type MOS transistor
103
and an n-type MOS transistor
105
, and a CMOS circuit which constitutes a low potential cell (VDDL cell)
107
which is driven by a low potential power supply voltage (VDDL) and consists of a p-type MOS transistor
109
and an n-type MOS transistor
111
. A signal which is output from the low potential cell
107
is input into the high potential cell
101
. As shown in
FIG. 1
, a connection between an output node of the low potential cell
107
and an input node of the high potential cell
101
is called a power supply voltage illegal connection.
FIG. 1
is an equivalent circuit diagram showing a part of a dual power supply integrated circuit employing two power supply voltages. As shown in
FIG. 1
, the dual power supply integrated circuit is composed of a CMOS circuit which constitutes a high potential cell (VDDH cell)
101
which is driven by a high potential power supply voltage (VDDH) and consists of a p-type MOS transistor
103
and an n-type MOS transistor
105
, and a CMOS circuit which constitutes a low potential cell (VDDL cell)
107
which is driven by a low potential power supply voltage (VDDL) and consists of a p-type MOS transistor
109
and an n-type MOS transistor
111
. A signal which is output from the low potential cell
107
is input into the high potential cell
101
. As shown in
FIG. 1
, a connection between an output node of the low potential cell
107
and an input node of the high potential cell
101
is called a power supply voltage illegal connection.
In
FIG. 1
, when the high potential cell
101
receives a low level (GND level) signal from the low potential cell
107
, the p-type MOS transistor
103
is brought into a conduction state and the n-type MOS transistor
105
is brought into a non-conduction state. In contrast, when the high potential cell
101
receives a high level (VDDL level) signal from the low potential cell
107
, the p-type MOS transistor
103
is brought into the non-conduction state and the n-type MOS transistor
105
is brought into the conduction state. That is, either of the p-type MOS transistor
103
and the n-type MOS transistor
105
is brought into the non-conduction state. However, a high level signal which is output from the low potential cell
107
is at a low potential power supply voltage (VDDL) level. Therefore, according to a threshold value voltage (Vthp) of the p-type MOS transistor
103
of the high potential cell
101
, such a situation is caused that the p-type MOS transistor
103
cannot be perfectly cut off. In other words, if
VDDL<VDDH−|Vthp| (1)
is satisfied, the p-type MOS transistor
103
cannot be cut off. As a result, a through current Is is flown from the high potential power supply voltage (VDDH) to ground potential (GND) via the p-type MOS transistor
103
and the n-type MOS transistor
105
. This through current Is causes increase of the power consumption of the circuit. In addition, there is a possibility that circuit performances become unstable.
Accordingly, in order to suppress the through current Is caused by the power supply voltage illegal connection, as shown in
FIG. 2
, a level converter cell (LC cell)
113
is provided between an output node of the low potential cell
107
and an input node of the high potential cell
101
, the high level output signal of the low potential cell
107
must be changed from the low potential power supply voltage (VDDL) level to the high potential power supply voltage (VDDH) level. However, insertion of level converter cells
113
is overhead of the power consumption in the circuit. Therefore, unnecessary level converter cells consume wastefully the power. For this reason, in order to reduce the power consumption in the circuit, the level converter cells must be placed only at locations corresponding to the power supply voltage illegal connection. In addition, it is preferable that the level converter cells are deleted from the redundant connection in which the level converter cells are placed despite that the level converter cells are not needed essentially.
However, in the prior art, there has been provided no approach which can decide locations corresponding to the above power supply voltage illegal connections and the redundant connections without fail in the stage of circuit design. Therefore, it has been impossible to reduce the power consumption in the circuit by inserting or deleting the level converter cells in the stage of circuit design.
SUMMARY OF THE INVENTION
The present invention has been made in light of the above circumstances, and it is an object of the present invention to provide a multi power supply integrated circuit evaluating system which is capable of detecting power supply voltage illegal connection, redundant connection, and potential redundant connection in the stage of circuit design, and a method of operating the same.
It is another object of the present invention to provide a multi power supply integrated circuit evaluating system which is capable of correcting automatically the detected power supply voltage illegal connection, the detected redundant connection, and the detected potential redundant connection to achieve lower power consumption of the multi power supply integrated circuit, and a method of operat
Kanazawa Masahiro
Usami Kimiyoshi
Foley & Lardner
Kabushiki Kaisha Toshiba
Phan Trong
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