Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-07-24
2001-01-09
Chan, Eddie P. (Department: 2751)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
06173365
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87103899, filed Mar. 17, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computers, and more particularly, to a cache memory system and a method for accessing this cache memory system, which allow the computer system to operate with high performance even though a low-speed tag RAM is used in the cache memory system.
2. Description of Related Art
In the use of computers, performance is a primary concern. A computer system's performance can be enhanced in various ways, such as by using a high-speed CPU instead of a low-speed one. In the past, the PC/XT-based IBM-compatible personal computers (PC) were driven by a system clock of only 4.77 MHz. Nowadays, however, most IBM-compatible PCs are running at 100 MHz or higher. The use of high-speed CPUs can undoubtedly increase the overall performance of the computer system. However, using a high-speed CPU also requires use of high-speed peripheral devices in conjunction with the high-speed CPU. If a low-speed peripheral device, such as a low-speed memory, is used in conjunction with high-speed CPU, the overall performance of the computer system is still unsatisfactorily low.
A computer system typically includes two types of memories: ROM (read-only memory) and RAM (random-access memory). The ROM is used to permanently store repeatedly used programs and data, such as the booting routines, while the RAM is used to store frequently updated or changed programs and data. ROMs are typically slower in speed than RAMs. Therefore, in operation, the programs stored in the ROM are customarily moved to the RAM after the computer has been booted. This scheme allows an increase in the performance of the computer system. Furthermore, there are two types of RAMs: SRAM (static random-access memory) and DRAM (dynamic random access memory). SRAMs are higher in speed than DRAMs. But since SRAMs are significantly smaller in packing density and more difficult to manufacture than DRAMs, DRAMs are more cost-effective to use than SRAMs. Therefore, although lower in speed, DRAMs are widely used as the primary memory on most computer systems.
Use of a high-speed CPU is used in conjunction with a low-speed DRAM gives rise to the problem of a performance bottleneck. A solution to this problem is to provide a so-called cache memory in addition to the primary memory. In this solution, low-speed DRAMs are used as the primary memory of the computer system, while high-speed SRAMs are used as the cache memory. The cache memory stores the most frequently accessed blocks of programs and data from the primary memory. When requesting data, the CPU first checks whether the requested data are stored in the cache memory; if not, the CPU then turns the request to the primary memory. The use of cache memory can significantly increase the overall performance of the computer system. However, since the cache memory is much smaller in capacity than the primary memory, the requested data may not be always found in the cache memory. It is called a hit if the requested data are currently stored in the cache memory and a miss if not. The term “cache hit rate” refers to the number of times that an operand requested by the CPU is found in the cache memory. Therefore, the cache hit rate is a measure of the performance of a cache algorithm. In the case of IBM-compatible PCs, if the cache memory is larger than 512 KB (kilobyte) in capacity, the cache hit rate can be higher than 90%, which can considerably help improve the overall performance of the computer system. Furthermore, the use of a new type of SRAM, called PBSRAM (pipelined burst static random-access memory), as the cache memory can further increase the overall performance of the computer system.
FIG. 1
is a schematic diagram showing the architecture of a conventional cache memory system used in conjunction with a computer system. The cache memory system here is the part enclosed in a dashed box indicated by the reference numeral
110
. As shown, the cache memory system
110
includes a cache memory module
111
, which includes a data RAM unit
113
and a tag RAM unit
114
, and a cache control circuit
112
. All of the constituent components of the cache memory system
110
are coupled via a common data bus
150
to the CPU
120
and the primary memory unit
140
of the computer system for data exchange. The cache control circuit
112
is used to control access to the cache memory module
111
in response to any read/write requests from the CPU
120
. When a block of data in the primary memory unit
140
is placed in the cache memory module
111
, the data values thereof are stored in the data RAM unit
113
while the tag values used to help map the addresses in the data RAM unit
113
to the primary memory unit
140
are stored in the tag RAM unit
114
. Moreover, the tag RAM unit
114
stores a so-called “dirty bit” that is used to indicate whether the data currently stored in the data RAM unit
113
have been updated by the CPU
120
.
The scheme for mapping the data and address values from the primary memory unit
140
to the cache memory module
111
is depicted in FIG.
2
A. As mentioned earlier, when a block of data in the primary memory unit
140
is placed in the cache memory module
111
, the data values thereof are stored in the data RAM unit
113
while the tag values are stored in the tag RAM unit
114
. As shown in
FIG. 2B
, the physical addresses of this block of data can be determined by combining the tag values with the index values. When the CPU
120
references a particular address in the primary memory unit
140
, the value of that address can be directly mapped by a direct mapping method to the cache memory module
111
so as to fetch the requested data from the mapped addresses in the cache memory module
111
.
To determine whether the request from the CPU is a hit or a miss, the address values issued by the CPU
120
are compared with the contents stored in the tag RAM unit
114
. If matched, the requested data are currently stored in the cache memory module
111
; otherwise, the requested data are not stored in the cache memory module
111
and access is turned to the primary memory unit
140
. The access speed to the tag RAM unit
114
is therefore one of the primary factors that affect the overall performance of the computer system.
FIG. 3
is a flow diagram showing the procedural steps involved in a conventional cache read algorithm for reading data from the cache memory system
110
. This algorithm is carried out by the cache control circuit
112
in response to a data read request signal from the CPU
120
.
As shown, in the initial step
310
, the CPU
120
issues a data read request signal to the cache memory system
110
.
In the next step
311
, the cache memory system
110
checks whether the data read request signal is a hit or a miss to the cache memory system
110
.
If it is a hit, the procedure goes to step
320
, in which the requested data are transferred from the cache memory module
111
to the CPU
120
.
Otherwise, if it is a miss, the procedure goes to step
313
, in which the cache control circuit
112
checks whether the data currently stored in the cache memory module
111
have been updated.
If not updated, the procedure goes to step
332
in which the data requested by the CPU
120
are moved from the primary memory unit
140
to the cache memory module
111
, and subsequently transferred from the cache memory module
111
to the CPU
120
. This completes the response to the request from the CPU
120
.
Otherwise, if updated, the procedure goes to step
330
in which the updated data are moved from the cache memory module
111
to the primary memory unit
140
. The procedure then goes on to step
331
in which the data requested by the CPU
120
are moved from the primary memory unit
140
to the cache memory module
111
, and subsequently transferred from the ca
Chan Eddie P.
Thomas Kayden Horstemeyer & Risley
Verbrugge Kevin
VIA Technologies Inc.
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